AES/MASKED Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	66.456us	1	1	100.00
V1	smoke	aes_smoke	25.000s	731.023us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	153.768us	5	5	100.00
V1	csr_rw	aes_csr_rw	10.000s	53.629us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	520.610us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	214.743us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	85.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	10.000s	53.629us	20	20	100.00
		aes_csr_aliasing	10.000s	214.743us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	25.000s	731.023us	50	50	100.00
		aes_config_error	17.000s	428.368us	50	50	100.00
		aes_stress	51.000s	1.407ms	50	50	100.00
V2	key_length	aes_smoke	25.000s	731.023us	50	50	100.00
		aes_config_error	17.000s	428.368us	50	50	100.00
		aes_stress	51.000s	1.407ms	50	50	100.00
V2	back2back	aes_stress	51.000s	1.407ms	50	50	100.00
		aes_b2b	55.000s	846.977us	50	50	100.00
V2	backpressure	aes_stress	51.000s	1.407ms	50	50	100.00
V2	multi_message	aes_smoke	25.000s	731.023us	50	50	100.00
		aes_config_error	17.000s	428.368us	50	50	100.00
		aes_stress	51.000s	1.407ms	50	50	100.00
		aes_alert_reset	33.000s	3.050ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	231.291us	50	50	100.00
		aes_config_error	17.000s	428.368us	50	50	100.00
		aes_alert_reset	33.000s	3.050ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.583m	4.296ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	1.300m	3.800ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	33.000s	3.050ms	50	50	100.00
V2	stress	aes_stress	51.000s	1.407ms	50	50	100.00
V2	sideload	aes_stress	51.000s	1.407ms	50	50	100.00
		aes_sideload	35.000s	4.991ms	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	87.559us	50	50	100.00
V2	stress_all	aes_stress_all	1.333m	7.156ms	10	10	100.00
V2	alert_test	aes_alert_test	20.000s	60.147us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	78.735us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	78.735us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	153.768us	5	5	100.00
		aes_csr_rw	10.000s	53.629us	20	20	100.00
		aes_csr_aliasing	10.000s	214.743us	5	5	100.00
		aes_same_csr_outstanding	3.050m	10.028ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	153.768us	5	5	100.00
		aes_csr_rw	10.000s	53.629us	20	20	100.00
		aes_csr_aliasing	10.000s	214.743us	5	5	100.00
		aes_same_csr_outstanding	3.050m	10.028ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.167m	2.338ms	50	50	100.00
V2S	fault_inject	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	14.000s	455.177us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	1.189ms	5	5	100.00
		aes_tl_intg_err	9.000s	1.324ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	1.324ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	33.000s	3.050ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	25.000s	731.023us	50	50	100.00
		aes_stress	51.000s	1.407ms	50	50	100.00
		aes_alert_reset	33.000s	3.050ms	50	50	100.00
		aes_core_fi	53.000s	10.005ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	12.000s	78.695us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	98.088us	50	50	100.00
		aes_stress	51.000s	1.407ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	51.000s	1.407ms	50	50	100.00
		aes_sideload	35.000s	4.991ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	98.088us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	98.088us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	98.088us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	98.088us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	98.088us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	51.000s	1.407ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	51.000s	1.407ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.550m	3.346ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.550m	3.346ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.009ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.550m	3.346ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	33.000s	3.050ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_ctr_fi	8.000s	223.869us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.550m	3.346ms	50	50	100.00
		aes_control_fi	29.000s	10.026ms	281	300	93.67
		aes_cipher_fi	48.000s	10.009ms	341	350	97.43
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.367m	26.116ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.59	98.94	97.34	99.45	95.97	97.64	100.00	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 15 failures.
  - 9.aes_control_fi.24049304760759661271519370023259852939437491649732183675902054853579609709990
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:61ff7e6e-5033-44d5-b315-30518e95873f
```
  - 14.aes_control_fi.23859959081420187049827313339798758684210752699116182289770034475801091240994
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job ID: smart:dc640429-e91c-49e2-b179-6e638b2b72fa
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 16.aes_cipher_fi.49421474627454938155480661117916284426388249443949966588721178429413297119565
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c7bc05aa-67e5-45fc-b08f-2d38d10f737c
```
  - 164.aes_cipher_fi.13724806010830009306996082440559064702982396490760956981989789753881706017096
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/164.aes_cipher_fi/latest/run.log
```
  Job ID: smart:674e02e0-f8a0-4d00-83a5-72676c5fc16b
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.114864530872183507927186099868456494589020849912467806048467335964719842130997
Line 892, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1561097939 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1561097939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.102350457183910501264884249567249229318722059583245798794316381132363136413933
Line 1620, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 890859528 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 890859528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 18.aes_core_fi.24516629782227617655522952462846750871271692446517010691364706784763820338726
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10100706406 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10100706406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_core_fi.22146834726068016795100150307041428612246623558673610280648080429996705952930
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010137461 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010137461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 5.aes_cipher_fi.103274768196281701492360857506969660629858872587505616864804674343525491197941
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009039677 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009039677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_cipher_fi.82573590171137286090916737114528014764293429653394620514472962750660186659346
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036604380 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036604380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 150.aes_control_fi.93769324886583687602041920913443983962060934932332087548011391677952240418292
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/150.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10037384255 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037384255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 181.aes_control_fi.56414694783856579219180498868535526278146640045821692013489488360473152231810
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/181.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015054304 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015054304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.107588349382965580265012290978339594275485506544502516014176973204797175244123
Line 723, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 346968506 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 346968506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.94086277134040227528925104341762677024545153307969558014264537581659292550366
Line 1202, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 979867477 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 979867477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 5.aes_same_csr_outstanding.85475254430278864801413163955462506732810285898892075824403207061171893745272
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10028088655 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x114eb984) == 0x0
  UVM_INFO @ 10028088655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 49.aes_core_fi.27598224239102503059232368425101585057173793750577312252041005373096514093235
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038184351 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038184351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```