AES/MASKED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	126.605us	1	1	100.00
V1	smoke	aes_smoke	20.000s	109.213us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	176.972us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	58.306us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	867.301us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	127.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	455.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	58.306us	20	20	100.00
		aes_csr_aliasing	5.000s	127.004us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	20.000s	109.213us	50	50	100.00
		aes_config_error	33.000s	1.129ms	50	50	100.00
		aes_stress	1.850m	6.261ms	50	50	100.00
V2	key_length	aes_smoke	20.000s	109.213us	50	50	100.00
		aes_config_error	33.000s	1.129ms	50	50	100.00
		aes_stress	1.850m	6.261ms	50	50	100.00
V2	back2back	aes_stress	1.850m	6.261ms	50	50	100.00
		aes_b2b	58.000s	602.357us	50	50	100.00
V2	backpressure	aes_stress	1.850m	6.261ms	50	50	100.00
V2	multi_message	aes_smoke	20.000s	109.213us	50	50	100.00
		aes_config_error	33.000s	1.129ms	50	50	100.00
		aes_stress	1.850m	6.261ms	50	50	100.00
		aes_alert_reset	29.000s	964.830us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	56.442us	50	50	100.00
		aes_config_error	33.000s	1.129ms	50	50	100.00
		aes_alert_reset	29.000s	964.830us	50	50	100.00
V2	trigger_clear_test	aes_clear	51.000s	1.736ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	333.351us	1	1	100.00
V2	reset_recovery	aes_alert_reset	29.000s	964.830us	50	50	100.00
V2	stress	aes_stress	1.850m	6.261ms	50	50	100.00
V2	sideload	aes_stress	1.850m	6.261ms	50	50	100.00
		aes_sideload	17.000s	533.659us	50	50	100.00
V2	deinitialization	aes_deinit	40.000s	2.182ms	50	50	100.00
V2	stress_all	aes_stress_all	56.000s	10.638ms	10	10	100.00
V2	alert_test	aes_alert_test	28.000s	136.652us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	88.278us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	88.278us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	176.972us	5	5	100.00
		aes_csr_rw	7.000s	58.306us	20	20	100.00
		aes_csr_aliasing	5.000s	127.004us	5	5	100.00
		aes_same_csr_outstanding	13.000s	126.876us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	176.972us	5	5	100.00
		aes_csr_rw	7.000s	58.306us	20	20	100.00
		aes_csr_aliasing	5.000s	127.004us	5	5	100.00
		aes_same_csr_outstanding	13.000s	126.876us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.067m	3.882ms	50	50	100.00
V2S	fault_inject	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	138.942us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.298ms	5	5	100.00
		aes_tl_intg_err	6.000s	167.369us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	167.369us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	29.000s	964.830us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	109.213us	50	50	100.00
		aes_stress	1.850m	6.261ms	50	50	100.00
		aes_alert_reset	29.000s	964.830us	50	50	100.00
		aes_core_fi	50.000s	4.641ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	146.949us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	84.137us	50	50	100.00
		aes_stress	1.850m	6.261ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.850m	6.261ms	50	50	100.00
		aes_sideload	17.000s	533.659us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	84.137us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	84.137us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	84.137us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	84.137us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	84.137us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.850m	6.261ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.850m	6.261ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	20.000s	2.145ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	20.000s	2.145ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	20.000s	2.145ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	29.000s	964.830us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	122.777us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	20.000s	2.145ms	49	50	98.00
		aes_control_fi	49.000s	10.005ms	276	300	92.00
		aes_cipher_fi	49.000s	10.006ms	334	350	95.43
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.217m	14.862ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.52	98.90	97.23	99.42	95.77	97.72	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 20 failures.
  - 3.aes_control_fi.23361970782791213982688868966508769738751281078977785568570248491431122464545
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:6bc4b467-e96f-4516-b687-fe3f353ce2d6
```
  - 24.aes_control_fi.2563105505627148847021771214735297470383875897353837886551249922905974459955
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:69695e6c-7dcf-473b-8def-c3c0526414a5
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 8 failures.
  - 7.aes_cipher_fi.9539053938825507713271163208580181070676903142712767486878043237694698108154
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:567c1072-7a20-452f-88e3-84ed6c7ec487
```
  - 23.aes_cipher_fi.68604739421086342118553997342258689239996748558241820897900645220047749986826
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6455fc82-2922-41d9-89ce-749c9e8f296d
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.52365848713000113647188546743315196322753374054353946097887699346442864272190
Line 607, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 231541761 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 231541761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.97123067944468676855084039905458510300847742783125706815193102759978956077451
Line 733, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 599207235 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 599207235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 25.aes_cipher_fi.110096470028831851016653733608205142720321057695986277074661323143948195716305
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011324774 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011324774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.aes_cipher_fi.54850201361573385258402698791324140852032634964470649960149159590291873656576
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015479868 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015479868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 118.aes_control_fi.78456236502230134045364924155229245582427706398328065673773232294624791895618
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/118.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017451762 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017451762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 210.aes_control_fi.41324197957444402644167446923160489623241474538316820590613959253152161945404
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/210.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013183302 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013183302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.99475852852499056010984680226812070247136018058638917083776056351150395038878
Line 1054, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1099615351 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1099615351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.3208741946768571813017248745095653225341373910122155147634022245338363004575
Line 1627, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1417623859 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1417623859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 8.aes_fi.61751079914383560963901231136340765068390666197715713067749323220023712202714
    Line 14767, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_fi/latest/run.log
```
  UVM_FATAL @  76586416 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  76586416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 60.aes_core_fi.52431123946425371380665503071612413364305160128809154009968173313884688854199
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10033030070 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033030070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```