AES/MASKED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	259.206us	1	1	100.00
V1	smoke	aes_smoke	17.000s	1.626ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	65.082us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	272.338us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.548ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	166.421us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	85.523us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	272.338us	20	20	100.00
		aes_csr_aliasing	5.000s	166.421us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	17.000s	1.626ms	50	50	100.00
		aes_config_error	15.000s	497.452us	50	50	100.00
		aes_stress	49.000s	1.471ms	50	50	100.00
V2	key_length	aes_smoke	17.000s	1.626ms	50	50	100.00
		aes_config_error	15.000s	497.452us	50	50	100.00
		aes_stress	49.000s	1.471ms	50	50	100.00
V2	back2back	aes_stress	49.000s	1.471ms	50	50	100.00
		aes_b2b	42.000s	562.971us	50	50	100.00
V2	backpressure	aes_stress	49.000s	1.471ms	50	50	100.00
V2	multi_message	aes_smoke	17.000s	1.626ms	50	50	100.00
		aes_config_error	15.000s	497.452us	50	50	100.00
		aes_stress	49.000s	1.471ms	50	50	100.00
		aes_alert_reset	32.000s	1.203ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	67.773us	50	50	100.00
		aes_config_error	15.000s	497.452us	50	50	100.00
		aes_alert_reset	32.000s	1.203ms	50	50	100.00
V2	trigger_clear_test	aes_clear	26.000s	917.181us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	264.147us	1	1	100.00
V2	reset_recovery	aes_alert_reset	32.000s	1.203ms	50	50	100.00
V2	stress	aes_stress	49.000s	1.471ms	50	50	100.00
V2	sideload	aes_stress	49.000s	1.471ms	50	50	100.00
		aes_sideload	9.000s	97.360us	50	50	100.00
V2	deinitialization	aes_deinit	42.000s	1.389ms	50	50	100.00
V2	stress_all	aes_stress_all	1.383m	2.378ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	56.955us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	81.444us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	81.444us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	65.082us	5	5	100.00
		aes_csr_rw	3.000s	272.338us	20	20	100.00
		aes_csr_aliasing	5.000s	166.421us	5	5	100.00
		aes_same_csr_outstanding	4.000s	823.549us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	65.082us	5	5	100.00
		aes_csr_rw	3.000s	272.338us	20	20	100.00
		aes_csr_aliasing	5.000s	166.421us	5	5	100.00
		aes_same_csr_outstanding	4.000s	823.549us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	31.000s	1.980ms	50	50	100.00
V2S	fault_inject	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	146.566us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	494.261us	5	5	100.00
		aes_tl_intg_err	6.000s	291.685us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	291.685us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	32.000s	1.203ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	17.000s	1.626ms	50	50	100.00
		aes_stress	49.000s	1.471ms	50	50	100.00
		aes_alert_reset	32.000s	1.203ms	50	50	100.00
		aes_core_fi	16.000s	656.309us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	59.044us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	163.010us	50	50	100.00
		aes_stress	49.000s	1.471ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	49.000s	1.471ms	50	50	100.00
		aes_sideload	9.000s	97.360us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	163.010us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	163.010us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	163.010us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	163.010us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	163.010us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	49.000s	1.471ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	49.000s	1.471ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.133m	5.259ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.133m	5.259ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.133m	5.259ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	32.000s	1.203ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_ctr_fi	9.000s	77.005us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.133m	5.259ms	50	50	100.00
		aes_control_fi	34.000s	10.009ms	284	300	94.67
		aes_cipher_fi	49.000s	10.006ms	339	350	96.86
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.167m	2.508ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1564	1602	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.56	98.91	97.25	99.45	95.84	97.72	100.00	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 14 failures.
  - 19.aes_control_fi.96836096191988291751601935922064829427311751782968890430298295002933761843928
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:1161b626-be40-4029-940c-e0319d6d7103
```
  - 28.aes_control_fi.92606060211227462724045536761032892588310408702584052240926463974674118792117
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job ID: smart:8c155718-d958-4381-bd9c-8a7236fe6d62
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 2 failures.
  - 41.aes_cipher_fi.98817281484128310755126736709986904021929968353600796461634152497935899935323
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fd1b79a9-26d8-4ce5-9e72-6c44d575c2f9
```
  - 319.aes_cipher_fi.5454021187431251522889702009038047802298039851728551107832073467509846609637
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/319.aes_cipher_fi/latest/run.log
```
  Job ID: smart:aa9155bb-4e16-4084-a37e-7d119a1fd28b
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 28.aes_cipher_fi.49910817689504206321645207674330234605841085049744962910702506479116794374860
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022252407 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022252407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_cipher_fi.24862902894041671890326895270405378159447993003777356392655249633790677420062
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10053685275 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10053685275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.80141872989518303607668139240427829073257468387402244824813142010199899093627
Line 886, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1373494859 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1373494859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.21345358925952623206765439501167803278474537856977540888774758909864382360385
Line 467, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1015381907 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1015381907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.13080880196786817201254727779849014876617819654800681060068540338038824457474
Line 747, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 263930566 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 263930566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.91746435078900976270678109308910772747752993351965997009312620855951425856841
Line 1651, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1683523199 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1683523199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.51473155515080084198206093026500409063581633193501807812325734018549275646037
    Line 873, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2521657073 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2521657073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.aes_csr_mem_rw_with_rand_reset.55817355759372980609960045078976873896193451594788887913704404307105613160574
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 541558497 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 541558497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 107.aes_control_fi.77871258956543413895487150293365569430536735781420436552497541151256745825528
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008812236 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008812236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 215.aes_control_fi.60481190342421840235293660836040048886805032515639257383453383991148302192993
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/215.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018753688 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018753688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.1943655418505895721450302337186227537897680816268105967259306375462815744441
    Line 403, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1802716571 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1802716571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.88059989031285858252853886466700107314464935529733667734050376098684248030904
    Line 883, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5438438006 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5438438006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```