AES/MASKED Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	137.940us	1	1	100.00
V1	smoke	aes_smoke	36.000s	1.055ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	60.460us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	215.692us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	6.656ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	182.737us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	106.197us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	215.692us	20	20	100.00
		aes_csr_aliasing	10.000s	182.737us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	36.000s	1.055ms	50	50	100.00
		aes_config_error	9.000s	233.723us	50	50	100.00
		aes_stress	12.000s	156.600us	50	50	100.00
V2	key_length	aes_smoke	36.000s	1.055ms	50	50	100.00
		aes_config_error	9.000s	233.723us	50	50	100.00
		aes_stress	12.000s	156.600us	50	50	100.00
V2	back2back	aes_stress	12.000s	156.600us	50	50	100.00
		aes_b2b	45.000s	638.235us	50	50	100.00
V2	backpressure	aes_stress	12.000s	156.600us	50	50	100.00
V2	multi_message	aes_smoke	36.000s	1.055ms	50	50	100.00
		aes_config_error	9.000s	233.723us	50	50	100.00
		aes_stress	12.000s	156.600us	50	50	100.00
		aes_alert_reset	34.000s	1.216ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	254.891us	50	50	100.00
		aes_config_error	9.000s	233.723us	50	50	100.00
		aes_alert_reset	34.000s	1.216ms	50	50	100.00
V2	trigger_clear_test	aes_clear	25.000s	650.573us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	22.000s	418.667us	1	1	100.00
V2	reset_recovery	aes_alert_reset	34.000s	1.216ms	50	50	100.00
V2	stress	aes_stress	12.000s	156.600us	50	50	100.00
V2	sideload	aes_stress	12.000s	156.600us	50	50	100.00
		aes_sideload	40.000s	1.619ms	50	50	100.00
V2	deinitialization	aes_deinit	56.000s	1.801ms	50	50	100.00
V2	stress_all	aes_stress_all	6.433m	106.274ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	88.765us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	84.801us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	84.801us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	60.460us	5	5	100.00
		aes_csr_rw	8.000s	215.692us	20	20	100.00
		aes_csr_aliasing	10.000s	182.737us	5	5	100.00
		aes_same_csr_outstanding	10.000s	95.712us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	60.460us	5	5	100.00
		aes_csr_rw	8.000s	215.692us	20	20	100.00
		aes_csr_aliasing	10.000s	182.737us	5	5	100.00
		aes_same_csr_outstanding	10.000s	95.712us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	299.979us	50	50	100.00
V2S	fault_inject	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	12.000s	76.069us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	1.350ms	5	5	100.00
		aes_tl_intg_err	16.000s	110.535us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	16.000s	110.535us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	34.000s	1.216ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	36.000s	1.055ms	50	50	100.00
		aes_stress	12.000s	156.600us	50	50	100.00
		aes_alert_reset	34.000s	1.216ms	50	50	100.00
		aes_core_fi	9.000s	295.328us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	82.060us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	63.012us	50	50	100.00
		aes_stress	12.000s	156.600us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	12.000s	156.600us	50	50	100.00
		aes_sideload	40.000s	1.619ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	63.012us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	63.012us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	63.012us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	63.012us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	63.012us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	12.000s	156.600us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	12.000s	156.600us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	1.919ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	1.919ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.009ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	1.919ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	34.000s	1.216ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_ctr_fi	10.000s	326.588us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	1.919ms	50	50	100.00
		aes_control_fi	30.000s	10.057ms	275	300	91.67
		aes_cipher_fi	50.000s	10.009ms	339	350	96.86
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.283m	23.818ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.57	98.93	97.32	99.44	95.93	97.72	98.52	99.11	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_cipher_fi has 6 failures.
  - 23.aes_cipher_fi.113411180805939117583509404841963168049235309503688235509229942842188949763211
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:65ff232e-55dc-4b7b-a85d-1f1281801dcb
```
  - 25.aes_cipher_fi.104283673086746298091784095066036548296215813013991269148693010682196373256280
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3bd56ae9-7077-44b1-b8d8-91c54e722d38
```
  - ... and 4 more failures.
- Test aes_control_fi has 20 failures.
  - 27.aes_control_fi.101052386783888668568835745026535659777124318928934007011348477853310018533498
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:5ff985af-9058-4910-87d1-d40281d4f29f
```
  - 34.aes_control_fi.29210238876151693980497722509250313147133869080341210993365297216660837200731
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:754cf1bd-5d61-493d-9a17-15fa86d0d654
```
  - ... and 18 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 11.aes_control_fi.7184803473524639837118730678105160636294410029266715129163078588972244644055
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008442062 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008442062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.aes_control_fi.2302674244657326742319245949115479899514002983105095661120942209434809042030
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10056571991 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10056571991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 33.aes_cipher_fi.22557735413168089559997321131519913499033950082821421547337347303071295954168
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010655127 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010655127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 118.aes_cipher_fi.12360541226865926804157769716247213555928896300582207621389389441692772280073
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/118.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009218623 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009218623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.44497753473592468395848404661672401210603891055444357859680184814130060741202
Line 1348, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 560418805 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 560418805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.62504097777424566134270357390102075178486498949392360337656395937614003909765
Line 1093, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 542601603 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 542601603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.54127569201537285817281787697279054573230324220771943683462844939910558201728
Line 1199, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23818270919 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 23818270919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.8251762806757916372466061324076496077654252356872366580992513526054408976356
Line 1648, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4108889974 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4108889974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.44690583152348209440008236786277681716272910858218375647985089589693818933814
    Line 447, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2572550284 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2572550284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.82879540582710118846128238233165271234898347626820772266151334628628904950663
    Line 370, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 238660151 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 238660151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```