AES/MASKED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	136.458us	1	1	100.00
V1	smoke	aes_smoke	11.000s	91.932us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	100.223us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	54.752us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	185.972us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.033m	10.040ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	146.605us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	54.752us	20	20	100.00
		aes_csr_aliasing	6.033m	10.040ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	11.000s	91.932us	50	50	100.00
		aes_config_error	19.000s	3.148ms	50	50	100.00
		aes_stress	1.617m	3.045ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	91.932us	50	50	100.00
		aes_config_error	19.000s	3.148ms	50	50	100.00
		aes_stress	1.617m	3.045ms	50	50	100.00
V2	back2back	aes_stress	1.617m	3.045ms	50	50	100.00
		aes_b2b	30.000s	1.065ms	50	50	100.00
V2	backpressure	aes_stress	1.617m	3.045ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	91.932us	50	50	100.00
		aes_config_error	19.000s	3.148ms	50	50	100.00
		aes_stress	1.617m	3.045ms	50	50	100.00
		aes_alert_reset	24.000s	580.847us	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	209.974us	50	50	100.00
		aes_config_error	19.000s	3.148ms	50	50	100.00
		aes_alert_reset	24.000s	580.847us	50	50	100.00
V2	trigger_clear_test	aes_clear	32.000s	2.086ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	172.788us	1	1	100.00
V2	reset_recovery	aes_alert_reset	24.000s	580.847us	50	50	100.00
V2	stress	aes_stress	1.617m	3.045ms	50	50	100.00
V2	sideload	aes_stress	1.617m	3.045ms	50	50	100.00
		aes_sideload	20.000s	535.612us	50	50	100.00
V2	deinitialization	aes_deinit	38.000s	1.098ms	50	50	100.00
V2	stress_all	aes_stress_all	4.617m	34.510ms	9	10	90.00
V2	alert_test	aes_alert_test	10.000s	68.835us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.215ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.215ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	100.223us	5	5	100.00
		aes_csr_rw	7.000s	54.752us	20	20	100.00
		aes_csr_aliasing	6.033m	10.040ms	4	5	80.00
		aes_same_csr_outstanding	53.000s	10.123ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	100.223us	5	5	100.00
		aes_csr_rw	7.000s	54.752us	20	20	100.00
		aes_csr_aliasing	6.033m	10.040ms	4	5	80.00
		aes_same_csr_outstanding	53.000s	10.123ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	2.717m	5.667ms	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	403.014us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	621.460us	5	5	100.00
		aes_tl_intg_err	6.000s	162.220us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	162.220us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	24.000s	580.847us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	91.932us	50	50	100.00
		aes_stress	1.617m	3.045ms	50	50	100.00
		aes_alert_reset	24.000s	580.847us	50	50	100.00
		aes_core_fi	29.000s	10.008ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	188.290us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	61.701us	50	50	100.00
		aes_stress	1.617m	3.045ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.617m	3.045ms	50	50	100.00
		aes_sideload	20.000s	535.612us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	61.701us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	61.701us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	61.701us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	61.701us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	61.701us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.617m	3.045ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.617m	3.045ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	696.000us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	696.000us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.022ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	696.000us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	24.000s	580.847us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_ctr_fi	7.000s	72.444us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	696.000us	50	50	100.00
		aes_control_fi	52.000s	10.005ms	282	300	94.00
		aes_cipher_fi	44.000s	10.022ms	342	350	97.71
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.267m	2.934ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1562	1602	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	11	84.62
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.54	98.92	97.27	99.42	95.79	97.72	97.78	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 13 failures.
  - 22.aes_control_fi.89488687831731413351843487382728439527292610851771619793559985368577554643883
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:e1e03d56-ba90-49aa-9da3-60f73eb4a967
```
  - 29.aes_control_fi.107472839371292333598105303278214684008309140787149604601093362824077322026468
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:4d8cf12a-1268-4f00-9401-3a3d8eef3b1a
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 3 failures.
  - 133.aes_cipher_fi.74150828102569605825314627379949894431499358075887463722507800826898691113813
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/133.aes_cipher_fi/latest/run.log
```
  Job ID: smart:331ebbba-9c3b-41cd-a7f5-e1d5b3e15865
```
  - 160.aes_cipher_fi.27187667760744653523896999289837329525578972709244610312981318258411638172214
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/160.aes_cipher_fi/latest/run.log
```
  Job ID: smart:461e6f38-fd19-40ca-bd9e-7a2c1d84eb55
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 63.aes_control_fi.53719206212322681462041600850591352021686750029650445767526682990264785714960
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006287243 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006287243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 240.aes_control_fi.8780506269665275832828616151512985335339045726938026875442524179290141589067
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/240.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005446377 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005446377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 108.aes_cipher_fi.2312922556405091270897212259416448535333301062453545611639584500747812124170
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/108.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10197975171 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10197975171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 111.aes_cipher_fi.19447454418746358776699169660586032741930866595041463850768322076530084022747
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/111.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022186120 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022186120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.39587636862193463016469230261719490397502207806521614166822580999910171835176
Line 1583, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5202379280 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5202379280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.86082231191461472523268202981481577278259410377743179690816301939823349452992
Line 1255, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 804733111 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 804733111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.8805601125939496155428185970155583736447040405444328964704641144671888708815
Line 1150, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2933604299 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2933604299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.18943393243007764446460306169154632329576114693828045468579349416097171920708
Line 1688, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 930922850 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 930922850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.20085916847047455349153280485823771247381991508078628461781223044428715011532
    Line 348, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1018475870 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1018475870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.12889284812932212074132603556197639309589481281959936036584763246647913009640
    Line 18072, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 3166902680 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3166902680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.9979118419221381660613650656370291280714605890875590073428350569504102317933
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157077061 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 157077061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 3.aes_csr_aliasing.7522312366664646931022813306787935490568705105561603064997697004068804880845
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10040377515 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x8718a084) == 0x0
  UVM_INFO @ 10040377515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 3.aes_same_csr_outstanding.103569061102014655545361238982516092642055947954382799474596572242424525152529
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10123340880 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1eb60084) == 0x0
  UVM_INFO @ 10123340880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 13.aes_core_fi.96680396062667476151846660422184492509278241938038603116704043331507356833022
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008040129 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008040129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```