AES/MASKED Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	94.853us	1	1	100.00
V1	smoke	aes_smoke	13.000s	1.154ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	93.553us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	50.287us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.012ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	131.686us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	102.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	50.287us	20	20	100.00
		aes_csr_aliasing	4.000s	131.686us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	1.154ms	50	50	100.00
		aes_config_error	11.000s	247.966us	50	50	100.00
		aes_stress	19.000s	2.193ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	1.154ms	50	50	100.00
		aes_config_error	11.000s	247.966us	50	50	100.00
		aes_stress	19.000s	2.193ms	50	50	100.00
V2	back2back	aes_stress	19.000s	2.193ms	50	50	100.00
		aes_b2b	1.167m	879.851us	50	50	100.00
V2	backpressure	aes_stress	19.000s	2.193ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	1.154ms	50	50	100.00
		aes_config_error	11.000s	247.966us	50	50	100.00
		aes_stress	19.000s	2.193ms	50	50	100.00
		aes_alert_reset	13.000s	473.748us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	51.221us	50	50	100.00
		aes_config_error	11.000s	247.966us	50	50	100.00
		aes_alert_reset	13.000s	473.748us	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	1.020ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	551.979us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	473.748us	50	50	100.00
V2	stress	aes_stress	19.000s	2.193ms	50	50	100.00
V2	sideload	aes_stress	19.000s	2.193ms	50	50	100.00
		aes_sideload	30.000s	860.707us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	511.061us	50	50	100.00
V2	stress_all	aes_stress_all	1.567m	9.948ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	91.048us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	247.569us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	247.569us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	93.553us	5	5	100.00
		aes_csr_rw	8.000s	50.287us	20	20	100.00
		aes_csr_aliasing	4.000s	131.686us	5	5	100.00
		aes_same_csr_outstanding	8.000s	73.744us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	93.553us	5	5	100.00
		aes_csr_rw	8.000s	50.287us	20	20	100.00
		aes_csr_aliasing	4.000s	131.686us	5	5	100.00
		aes_same_csr_outstanding	8.000s	73.744us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	473.596us	50	50	100.00
V2S	fault_inject	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	156.176us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	616.359us	5	5	100.00
		aes_tl_intg_err	9.000s	193.700us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	193.700us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	473.748us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	1.154ms	50	50	100.00
		aes_stress	19.000s	2.193ms	50	50	100.00
		aes_alert_reset	13.000s	473.748us	50	50	100.00
		aes_core_fi	1.450m	10.003ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	66.242us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	94.988us	50	50	100.00
		aes_stress	19.000s	2.193ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	2.193ms	50	50	100.00
		aes_sideload	30.000s	860.707us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	94.988us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	94.988us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	94.988us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	94.988us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	94.988us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	2.193ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	2.193ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.033m	6.794ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.033m	6.794ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.004ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.033m	6.794ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	473.748us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_ctr_fi	7.000s	229.977us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.033m	6.794ms	50	50	100.00
		aes_control_fi	45.000s	10.007ms	278	300	92.67
		aes_cipher_fi	50.000s	10.004ms	341	350	97.43
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.533m	278.671ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.49	98.86	97.14	99.37	95.84	97.72	97.78	99.11	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 18 failures.
  - 16.aes_control_fi.52570916800415937952715309774935538950788238712906212843621962670959283355698
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:c30a054e-a63d-4345-bb10-f58537b1e8be
```
  - 24.aes_control_fi.35863986778077049156021661091468329697488156467594771685595613172059395885512
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:97a32af9-0cb9-4e92-a2b0-21acc36361bb
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 2 failures.
  - 50.aes_cipher_fi.82289424164680984657850596448242179373993756279080729708691164472507438236330
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  Job ID: smart:36e721cc-1cfe-4611-949f-4bf89e83ec25
```
  - 140.aes_cipher_fi.52861682979314978366294244559430334146441401875824932191034091683543052098106
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/140.aes_cipher_fi/latest/run.log
```
  Job ID: smart:915cd8b5-8cd0-4668-9a35-c1bc1724d5ae
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 0.aes_cipher_fi.17121923310244114454736783815103349110957025954317355556887771498090514459748
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018347321 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018347321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_cipher_fi.56515427683515113002638859845527404471390842576348274821394987644157338202737
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10043013612 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043013612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.23578856013715146701048264544721858870413803025352046243561313439428100298349
Line 1698, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2844372450 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2844372450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.56946930384279877374734516607260098368138729810949326729662315222506756603854
Line 1070, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1527939586 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1527939586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 8.aes_core_fi.1661446127235685980975046711039968496296880879419170200814651254388085573294
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025712754 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025712754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_core_fi.71457307761153486375854592805077110247877257648659976782032487867488087470653
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013894487 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013894487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 75.aes_control_fi.38428217205199333882798065866177768894275902967505193744493284590040037248379
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014632137 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014632137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.aes_control_fi.51155931167606710008516186155603843000720070725001212015370347112199707311062
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010612221 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010612221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.23780630509818054244931180144720946006541428018633054270564479374389268666794
Line 779, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2380622376 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2380622376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.114940508472262698436294688499147337915071907023529573163887822207099100709731
Line 1924, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 278670556283 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 278670556283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.64002687336812581341456091079710186566213035095404709003148336619509527627054
    Line 384, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 253377763 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 253377763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```