AES/MASKED Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	90.741us	1	1	100.00
V1	smoke	aes_smoke	18.000s	68.210us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	53.184us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	58.775us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	597.011us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	287.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	109.429us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	58.775us	20	20	100.00
		aes_csr_aliasing	6.000s	287.980us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	18.000s	68.210us	50	50	100.00
		aes_config_error	1.050m	2.107ms	50	50	100.00
		aes_stress	57.000s	2.009ms	50	50	100.00
V2	key_length	aes_smoke	18.000s	68.210us	50	50	100.00
		aes_config_error	1.050m	2.107ms	50	50	100.00
		aes_stress	57.000s	2.009ms	50	50	100.00
V2	back2back	aes_stress	57.000s	2.009ms	50	50	100.00
		aes_b2b	31.000s	424.826us	50	50	100.00
V2	backpressure	aes_stress	57.000s	2.009ms	50	50	100.00
V2	multi_message	aes_smoke	18.000s	68.210us	50	50	100.00
		aes_config_error	1.050m	2.107ms	50	50	100.00
		aes_stress	57.000s	2.009ms	50	50	100.00
		aes_alert_reset	42.000s	1.256ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	75.638us	50	50	100.00
		aes_config_error	1.050m	2.107ms	50	50	100.00
		aes_alert_reset	42.000s	1.256ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.533m	13.030ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	2.315ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	42.000s	1.256ms	50	50	100.00
V2	stress	aes_stress	57.000s	2.009ms	50	50	100.00
V2	sideload	aes_stress	57.000s	2.009ms	50	50	100.00
		aes_sideload	1.667m	3.492ms	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	217.560us	50	50	100.00
V2	stress_all	aes_stress_all	16.550m	25.789ms	10	10	100.00
V2	alert_test	aes_alert_test	17.000s	82.273us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	513.952us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	513.952us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	53.184us	5	5	100.00
		aes_csr_rw	8.000s	58.775us	20	20	100.00
		aes_csr_aliasing	6.000s	287.980us	5	5	100.00
		aes_same_csr_outstanding	6.000s	140.419us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	53.184us	5	5	100.00
		aes_csr_rw	8.000s	58.775us	20	20	100.00
		aes_csr_aliasing	6.000s	287.980us	5	5	100.00
		aes_same_csr_outstanding	6.000s	140.419us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	46.000s	1.460ms	50	50	100.00
V2S	fault_inject	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	246.227us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.091ms	5	5	100.00
		aes_tl_intg_err	9.000s	187.819us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	187.819us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	42.000s	1.256ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	68.210us	50	50	100.00
		aes_stress	57.000s	2.009ms	50	50	100.00
		aes_alert_reset	42.000s	1.256ms	50	50	100.00
		aes_core_fi	1.367m	10.010ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	60.281us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	21.000s	58.336us	50	50	100.00
		aes_stress	57.000s	2.009ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	57.000s	2.009ms	50	50	100.00
		aes_sideload	1.667m	3.492ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	21.000s	58.336us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	21.000s	58.336us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	21.000s	58.336us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	21.000s	58.336us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	21.000s	58.336us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	57.000s	2.009ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	57.000s	2.009ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	1.533ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	1.533ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.008ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	1.533ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	42.000s	1.256ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_ctr_fi	24.000s	64.226us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	1.533ms	50	50	100.00
		aes_control_fi	46.000s	10.012ms	280	300	93.33
		aes_cipher_fi	49.000s	10.008ms	336	350	96.00
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	13.033m	57.505ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.57	98.94	97.34	99.45	95.77	97.72	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_cipher_fi has 7 failures.
  - 16.aes_cipher_fi.69854618732250575602027826648774160484840281689227527999819383719146586529875
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0fe559b3-8a70-493e-924c-ca7edf863f5e
```
  - 44.aes_cipher_fi.102929410339935630515867386808811131101917923105524840688821455151973050995317
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  Job ID: smart:06ad3e17-d438-4018-ab91-ad978d6136b5
```
  - ... and 5 more failures.
- Test aes_control_fi has 13 failures.
  - 38.aes_control_fi.51209026765107551978232704883429993776128292605309018590690767559586340640374
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  Job ID: smart:b45dfde4-744f-492f-b71c-706cdcce79b7
```
  - 40.aes_control_fi.27862329191412154219617931717011723996183730511325223545925262432106569846135
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:d77c84af-9322-4cb5-b261-09522d0ba769
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 34.aes_control_fi.94535572958805868168888145744357921966540051722125791739826048488298134099171
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10042587373 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042587373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_control_fi.57022990245284553092824244270093156613786088949652787097977662457423900677427
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021436848 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021436848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 35.aes_cipher_fi.66895636386064540756906589993582770730533763716540726692266750362350355936352
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013691440 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013691440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 148.aes_cipher_fi.9849221544745693413436054185959552049670819223005220859512787977832286768126
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/148.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014443751 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014443751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.65842944601877513179355793938295585223754827523573604280021166538545829911889
Line 1165, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7521420837 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7521420837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.58872137237452346941336853885207505331469087055272989833848274005542853354709
Line 582, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4462347897 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4462347897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

5.aes_stress_all_with_rand_reset.68065094964348044477853953126821657340429948041551589608107837154037047546762
Line 910, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 496701202 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 496701202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.112897117173777394814602268910062594954464634490424778502866438135642274770894
Line 1374, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2675026676 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2675026676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.50979658793651344201999511510003135453091912231518344154078638378895100084547
    Line 503, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1494658056 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1494658056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.aes_csr_mem_rw_with_rand_reset.86345911769381154019772540267424515054830661377477669458634876283142008925323
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108714505 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108714505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 40.aes_core_fi.43287907954512116071234427511156158109869124341278422179416053660493102420265
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009914573 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009914573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.25133656479875456006456921505449932765448864962157826536488675341745747290288
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013269801 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013269801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.14593890703104841909699755309106807340055869223670291201350729776356545658571
    Line 625, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1944507893 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1944507893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```