9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 4.000s | 125.813us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 13.000s | 52.512us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 10.000s | 1.406ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 1.696ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 12.000s | 99.079us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 13.000s | 52.512us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 5.000s | 1.696ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 54 | 106 | 50.94 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 6.000s | 329.491us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 6.000s | 329.491us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 4.000s | 125.813us | 5 | 5 | 100.00 |
| aes_csr_rw | 13.000s | 52.512us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 5.000s | 1.696ms | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 107.277us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 4.000s | 125.813us | 5 | 5 | 100.00 |
| aes_csr_rw | 13.000s | 52.512us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 5.000s | 1.696ms | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 107.277us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 13.000s | 65.408us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 9.000s | 709.610us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 9.000s | 709.610us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 8.000s | 86.294us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 154 | 1602 | 9.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 83.99 | 99.38 | 98.15 | 99.87 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.88015195695256577653752554595211853036426315515051802413924421115610635979578
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.108675995862754871006056742923750163142724160974330104766027094790831749753471
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.59395609676655939452106548550723422143963955977856215236929382581765333628671
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.49280421866324914943030920889351217583872577413776164153148247620822793846106
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.52871533578294042299855261892214595953408953549394985144614897542879594439343
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.68020452082015436318809592064110306498873929668885445179379833764415964938823
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.20247397682176166463734820488688504835353433197354297571511420152640192417415
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.113744146323162942482041721152231848507342570010488180056119224218564416040568
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.58583155417826318332113295304998784223665505878870918698861725457795486983248
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.57477335308374586122565352825281865818980385694965702878641851298964621360935
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.68338575901111011703054261828771947757435006678979229884482036105106875460087
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.52252846989353491989648780158390264489948410777923027343261509939029790363940
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.21264652123497741044467668691922935067319158067598076157819590896970454741593
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.45410730752682838181088376106017853787268038829988994421505812861888695861678
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.52918438465290782298693824348957726194886737918280039514468382953747467730180
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.81884585132989605426581763696712982527822420050137110395641659544452392756956
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
2.aes_csr_mem_rw_with_rand_reset.7439398343429495597956739176425247733831603309271503854748112609925250873290
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 107137892 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107137892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---