AES/MASKED Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	183.398us	1	1	100.00
V1	smoke	aes_smoke	13.000s	447.024us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	89.214us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	282.922us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	458.015us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	155.086us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	213.993us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	282.922us	20	20	100.00
		aes_csr_aliasing	5.000s	155.086us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	13.000s	447.024us	50	50	100.00
		aes_config_error	42.000s	1.517ms	50	50	100.00
		aes_stress	47.000s	5.270ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	447.024us	50	50	100.00
		aes_config_error	42.000s	1.517ms	50	50	100.00
		aes_stress	47.000s	5.270ms	50	50	100.00
V2	back2back	aes_stress	47.000s	5.270ms	50	50	100.00
		aes_b2b	31.000s	1.175ms	50	50	100.00
V2	backpressure	aes_stress	47.000s	5.270ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	447.024us	50	50	100.00
		aes_config_error	42.000s	1.517ms	50	50	100.00
		aes_stress	47.000s	5.270ms	50	50	100.00
		aes_alert_reset	2.200m	4.866ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	144.683us	50	50	100.00
		aes_config_error	42.000s	1.517ms	50	50	100.00
		aes_alert_reset	2.200m	4.866ms	50	50	100.00
V2	trigger_clear_test	aes_clear	4.167m	6.855ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	6.152ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.200m	4.866ms	50	50	100.00
V2	stress	aes_stress	47.000s	5.270ms	50	50	100.00
V2	sideload	aes_stress	47.000s	5.270ms	50	50	100.00
		aes_sideload	11.000s	1.227ms	50	50	100.00
V2	deinitialization	aes_deinit	1.600m	3.376ms	50	50	100.00
V2	stress_all	aes_stress_all	2.533m	5.662ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	140.733us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	19.000s	64.339us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	19.000s	64.339us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	89.214us	5	5	100.00
		aes_csr_rw	13.000s	282.922us	20	20	100.00
		aes_csr_aliasing	5.000s	155.086us	5	5	100.00
		aes_same_csr_outstanding	16.000s	10.320ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	89.214us	5	5	100.00
		aes_csr_rw	13.000s	282.922us	20	20	100.00
		aes_csr_aliasing	5.000s	155.086us	5	5	100.00
		aes_same_csr_outstanding	16.000s	10.320ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	32.000s	1.211ms	50	50	100.00
V2S	fault_inject	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	69.792us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	729.231us	5	5	100.00
		aes_tl_intg_err	9.000s	178.788us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	178.788us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.200m	4.866ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	447.024us	50	50	100.00
		aes_stress	47.000s	5.270ms	50	50	100.00
		aes_alert_reset	2.200m	4.866ms	50	50	100.00
		aes_core_fi	1.383m	10.112ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	65.633us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	53.441us	50	50	100.00
		aes_stress	47.000s	5.270ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	47.000s	5.270ms	50	50	100.00
		aes_sideload	11.000s	1.227ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	53.441us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	53.441us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	53.441us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	53.441us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	53.441us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	47.000s	5.270ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	47.000s	5.270ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.007ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	24.000s	1.703ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.200m	4.866ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_ctr_fi	13.000s	120.433us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	24.000s	1.703ms	50	50	100.00
		aes_control_fi	52.000s	10.005ms	280	300	93.33
		aes_cipher_fi	49.000s	10.007ms	337	350	96.29
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.633m	15.292ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.49	98.86	97.14	99.38	95.81	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 8 failures.
  - 6.aes_cipher_fi.59519885061466903638458732219243052607402722553201787772206266219747206490941
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dbb6b92f-8486-43a2-aa3b-c1ef55f20d93
```
  - 25.aes_cipher_fi.44590588978699916665822597633549745276790729644364183642292862921087399238940
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f8d02d1a-1a17-4e16-b2e8-1bfe31499b3c
```
  - ... and 6 more failures.
- Test aes_control_fi has 14 failures.
  - 30.aes_control_fi.47045501173902248893878993998973734255531427687389388297781002887104987969819
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:2be42fb2-3e74-47e6-a0b4-7abefc21a4e6
```
  - 32.aes_control_fi.2056187459471180213556878806327932024770648302186579365169248251014554169244
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:c0562686-c4f6-4e90-88c3-5c43713e3e08
```
  - ... and 12 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.58182684488227397196567585280225300963102585470194393688955641715728027704459
Line 1490, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8201106435 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8201106435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.42534990388683669933417460028933842340688198425668076959627245119849366652158
Line 1006, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3074355169 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3074355169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 100.aes_control_fi.65325182741156466759714399406845020233846546977442812864141228246739137748865
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10056066610 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10056066610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 149.aes_control_fi.49610778881962443776957056593339297337387744488713813905227642530600404372546
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/149.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006693708 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006693708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 8.aes_cipher_fi.39485795256972011979170533885731631442650494774432874464273475777217458002174
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011974747 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011974747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 81.aes_cipher_fi.109576404709069246409667037947653875857362514400257499692593505289933839023064
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/81.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007021460 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007021460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 3.aes_core_fi.105571654434962435392373193318615232378868357027540156398772012659266993834027
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006932251 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006932251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.100655803336955310792514912171788603964710224491040649167367878578390123154233
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10111953506 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10111953506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 0.aes_same_csr_outstanding.86641986956933945774143210362247982665856101511070852167140199649937023373429
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10320170665 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x85118e84) == 0x0
  UVM_INFO @ 10320170665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.85366129118879497939975800160035632761190952110529989764533560750721300190182
    Line 1118, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2296324012 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2296324012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.aes_csr_mem_rw_with_rand_reset.26016920670782988683888999034227675596684086550643290238752183679676370351047
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 213992956 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 213992956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```