AES/MASKED Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: `1f410ef5dc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	119.648us	1	1	100.00
V1	smoke	aes_smoke	24.000s	75.036us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	139.675us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	198.440us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.438ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	190.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	126.913us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	198.440us	20	20	100.00
		aes_csr_aliasing	5.000s	190.202us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	24.000s	75.036us	50	50	100.00
		aes_config_error	24.000s	718.417us	50	50	100.00
		aes_stress	44.000s	1.550ms	50	50	100.00
V2	key_length	aes_smoke	24.000s	75.036us	50	50	100.00
		aes_config_error	24.000s	718.417us	50	50	100.00
		aes_stress	44.000s	1.550ms	50	50	100.00
V2	back2back	aes_stress	44.000s	1.550ms	50	50	100.00
		aes_b2b	52.000s	722.617us	50	50	100.00
V2	backpressure	aes_stress	44.000s	1.550ms	50	50	100.00
V2	multi_message	aes_smoke	24.000s	75.036us	50	50	100.00
		aes_config_error	24.000s	718.417us	50	50	100.00
		aes_stress	44.000s	1.550ms	50	50	100.00
		aes_alert_reset	14.000s	5.471ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	66.816us	50	50	100.00
		aes_config_error	24.000s	718.417us	50	50	100.00
		aes_alert_reset	14.000s	5.471ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.717m	9.866ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.325ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	5.471ms	50	50	100.00
V2	stress	aes_stress	44.000s	1.550ms	50	50	100.00
V2	sideload	aes_stress	44.000s	1.550ms	50	50	100.00
		aes_sideload	30.000s	607.212us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	113.222us	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	3.952ms	9	10	90.00
V2	alert_test	aes_alert_test	9.000s	84.023us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	126.262us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	126.262us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	139.675us	5	5	100.00
		aes_csr_rw	4.000s	198.440us	20	20	100.00
		aes_csr_aliasing	5.000s	190.202us	5	5	100.00
		aes_same_csr_outstanding	5.000s	204.379us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	139.675us	5	5	100.00
		aes_csr_rw	4.000s	198.440us	20	20	100.00
		aes_csr_aliasing	5.000s	190.202us	5	5	100.00
		aes_same_csr_outstanding	5.000s	204.379us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.617m	3.961ms	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	108.699us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.093ms	5	5	100.00
		aes_tl_intg_err	6.000s	216.974us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	216.974us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	5.471ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	24.000s	75.036us	50	50	100.00
		aes_stress	44.000s	1.550ms	50	50	100.00
		aes_alert_reset	14.000s	5.471ms	50	50	100.00
		aes_core_fi	20.000s	301.729us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	93.627us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	61.122us	50	50	100.00
		aes_stress	44.000s	1.550ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	44.000s	1.550ms	50	50	100.00
		aes_sideload	30.000s	607.212us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	61.122us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	61.122us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	61.122us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	61.122us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	61.122us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	44.000s	1.550ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	44.000s	1.550ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	855.066us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	855.066us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.038ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	855.066us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	5.471ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_ctr_fi	13.000s	101.772us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	855.066us	50	50	100.00
		aes_control_fi	51.000s	10.129ms	277	300	92.33
		aes_cipher_fi	47.000s	10.038ms	340	350	97.14
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.367m	30.186ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	98.91	97.27	99.41	95.92	97.72	97.78	99.11	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 18 failures.
  - 4.aes_control_fi.66604940171287980071899568689099125621031695454028679936335116186093629624075
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:37a1c010-c613-4df0-99d7-6298fc092506
```
  - 26.aes_control_fi.77973033645912296108781138618885873379065634570790016554993341636195128300321
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:b9f357cc-dea6-46e3-930b-b20d9e660fb3
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 4 failures.
  - 54.aes_cipher_fi.42352228896793506483357648215178092944972207798603433646926672687656629205221
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ffb837d8-9806-4041-91bb-a0b52f4b197d
```
  - 232.aes_cipher_fi.44908826466243744099396986769726796579317882275186496601327738802210139455332
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/232.aes_cipher_fi/latest/run.log
```
  Job ID: smart:51beed67-565a-46c6-ac7c-819108404f43
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 149.aes_cipher_fi.63519147103733769396628496777761529698178591880220485790329301091164976200641
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/149.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013181421 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013181421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 212.aes_cipher_fi.94819476703924822748155326549828310311242625966838588863327157915228357042045
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/212.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10035321456 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035321456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.108128419983908809916092194523269510772070381326062712703893679138907382411728
Line 1512, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 984071402 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 984071402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.28111329312596335446844602836387996303062508936915416187384705369556864364755
Line 703, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30185947298 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 30185947298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 96.aes_control_fi.69091011279064261535887970689034021342543853308061048312911769181087744867086
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10128889079 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10128889079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 106.aes_control_fi.69156445458493446978819475442019055462838819968142029842657825187690210994414
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/106.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020848067 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020848067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.46083297449027021186844587805407949255851702399157671780910577687968018673999
Line 527, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2944636931 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2944636931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.92757569207483668159311691874149470938474907306172735700380264734334212211492
Line 1223, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1150868839 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1150868839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.81087436945337495485181495825203412929651961523318888437848041843262526498884
    Line 368, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 933762320 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 933762320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.60432723634512521047556755312522238953647336150231035732877256780758869594830
    Line 174819, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 1949982451 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1949942451 PS)
  UVM_ERROR @ 1949982451 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1949982451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.105366118126946295991702669709543607027047652884328906930887971671576978917220
    Line 354, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 924280493 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 924280493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```