AES/MASKED Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	85.728us	1	1	100.00
V1	smoke	aes_smoke	30.000s	1.644ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	63.409us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	78.407us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	15.000s	560.762us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	81.053us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	162.915us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	78.407us	20	20	100.00
		aes_csr_aliasing	8.000s	81.053us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	30.000s	1.644ms	50	50	100.00
		aes_config_error	16.000s	1.356ms	50	50	100.00
		aes_stress	14.000s	4.404ms	50	50	100.00
V2	key_length	aes_smoke	30.000s	1.644ms	50	50	100.00
		aes_config_error	16.000s	1.356ms	50	50	100.00
		aes_stress	14.000s	4.404ms	50	50	100.00
V2	back2back	aes_stress	14.000s	4.404ms	50	50	100.00
		aes_b2b	37.000s	451.641us	50	50	100.00
V2	backpressure	aes_stress	14.000s	4.404ms	50	50	100.00
V2	multi_message	aes_smoke	30.000s	1.644ms	50	50	100.00
		aes_config_error	16.000s	1.356ms	50	50	100.00
		aes_stress	14.000s	4.404ms	50	50	100.00
		aes_alert_reset	10.000s	525.718us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	221.231us	50	50	100.00
		aes_config_error	16.000s	1.356ms	50	50	100.00
		aes_alert_reset	10.000s	525.718us	50	50	100.00
V2	trigger_clear_test	aes_clear	38.000s	1.394ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	56.000s	2.491ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	525.718us	50	50	100.00
V2	stress	aes_stress	14.000s	4.404ms	50	50	100.00
V2	sideload	aes_stress	14.000s	4.404ms	50	50	100.00
		aes_sideload	1.050m	2.017ms	50	50	100.00
V2	deinitialization	aes_deinit	22.000s	1.366ms	50	50	100.00
V2	stress_all	aes_stress_all	1.200m	4.028ms	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	55.521us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	229.147us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	229.147us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	63.409us	5	5	100.00
		aes_csr_rw	8.000s	78.407us	20	20	100.00
		aes_csr_aliasing	8.000s	81.053us	5	5	100.00
		aes_same_csr_outstanding	14.000s	266.916us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	63.409us	5	5	100.00
		aes_csr_rw	8.000s	78.407us	20	20	100.00
		aes_csr_aliasing	8.000s	81.053us	5	5	100.00
		aes_same_csr_outstanding	14.000s	266.916us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.767m	4.611ms	49	50	98.00
V2S	fault_inject	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	110.935us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	817.124us	5	5	100.00
		aes_tl_intg_err	10.000s	177.625us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	177.625us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	525.718us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	30.000s	1.644ms	50	50	100.00
		aes_stress	14.000s	4.404ms	50	50	100.00
		aes_alert_reset	10.000s	525.718us	50	50	100.00
		aes_core_fi	1.467m	10.016ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	81.666us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.617us	50	50	100.00
		aes_stress	14.000s	4.404ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	4.404ms	50	50	100.00
		aes_sideload	1.050m	2.017ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.617us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.617us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.617us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.617us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.617us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	4.404ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	4.404ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	152.294us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	152.294us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.006ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	152.294us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	525.718us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_ctr_fi	6.000s	439.705us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	152.294us	50	50	100.00
		aes_control_fi	15.000s	10.022ms	281	300	93.67
		aes_cipher_fi	51.000s	10.006ms	343	350	98.00
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.550m	6.031ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.54	98.92	97.27	99.44	95.88	97.64	97.78	98.96	95.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 4 failures.
  - 33.aes_cipher_fi.32013440232694208819624269237712137461009107492309144247267631715457485888018
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  Job ID: smart:363a9d89-db5e-4752-8a82-2dfffdbc68a3
```
  - 119.aes_cipher_fi.56121231001193057462333749969474690403711525606492834823602314277139216150475
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/119.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ef6ad433-59bc-40b3-b8ee-29ac9cf00c5f
```
  - ... and 2 more failures.
- Test aes_control_fi has 18 failures.
  - 48.aes_control_fi.58357176387633201785786353924669762342829925623471182216404702626439066973510
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job ID: smart:78b50b74-b9a8-418a-958e-25d1a1c0a347
```
  - 58.aes_control_fi.35555543876336522152477906804454950882750502040085768892970379316604096284268
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job ID: smart:6eb9cf7e-87b5-40cc-a145-81cf6e0454c3
```
  - ... and 16 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.95726670780505777390424203050035242991576713136172897627771948614365059901878
Line 1281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5657600091 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5657600091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.111646194910013076892189380614088508835712023909251363592011985957660637768931
Line 416, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1988597494 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1988597494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.76590309712441059489057074773502408670214346132334942634435837529232743524393
Line 496, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 159958742 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 159958742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.16730329002066354899846670568514601140224554291403334558120834257200859133017
Line 920, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 437589575 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 437589575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 3.aes_core_fi.6636718168915617279160211262701776251318701178267147189812075061656908659565
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014354604 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014354604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_core_fi.46430602050850842246279100209249840416629481159443474934172711573186918751153
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015686593 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015686593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 137.aes_cipher_fi.20065931596762771803015447401479489278397373085707099231880165766987893753589
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/137.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10071367471 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10071367471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 185.aes_cipher_fi.29790220448391925900855198004424127313195779590123304064998375270922054234630
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/185.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006004435 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006004435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

8.aes_stress_all.1249590142712772089771761388484594127350788435765743404578951471316226697654
Line 3143, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 17829793 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 17808960 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 17829793 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 17808960 PS)
  UVM_ERROR @  17829793 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.aes_csr_mem_rw_with_rand_reset.45016008962411079364188466702363443999392018819851968245539462932541112954197
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 596007410 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 596007410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,846): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

20.aes_core_fi.77913870008262227842133311049674665709861283055224388809727509594562232683369
Line 311, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,846): (time 16350865 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 16330032 PS)
  UVM_ERROR @  16350865 ps: (aes_cipher_core.sv:846) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @  16350865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 48.aes_reseed.42643860726514204646843271004147690813912378925236581441695656311541729347832
    Line 5930, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_reseed/latest/run.log
```
  UVM_FATAL @ 794848971 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 794848971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 232.aes_control_fi.7791359173928662220282684213809500671030285559652803843592711753018340145392
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/232.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021923945 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021923945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```