AES/MASKED Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: `7773b039d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	63.296us	1	1	100.00
V1	smoke	aes_smoke	28.000s	1.454ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	18.000s	109.737us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	89.763us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	18.000s	323.701us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.083m	10.022ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	15.000s	137.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	89.763us	20	20	100.00
		aes_csr_aliasing	6.083m	10.022ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	28.000s	1.454ms	50	50	100.00
		aes_config_error	14.000s	87.482us	50	50	100.00
		aes_stress	18.000s	1.142ms	50	50	100.00
V2	key_length	aes_smoke	28.000s	1.454ms	50	50	100.00
		aes_config_error	14.000s	87.482us	50	50	100.00
		aes_stress	18.000s	1.142ms	50	50	100.00
V2	back2back	aes_stress	18.000s	1.142ms	50	50	100.00
		aes_b2b	33.000s	742.912us	50	50	100.00
V2	backpressure	aes_stress	18.000s	1.142ms	50	50	100.00
V2	multi_message	aes_smoke	28.000s	1.454ms	50	50	100.00
		aes_config_error	14.000s	87.482us	50	50	100.00
		aes_stress	18.000s	1.142ms	50	50	100.00
		aes_alert_reset	18.000s	204.746us	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	169.920us	50	50	100.00
		aes_config_error	14.000s	87.482us	50	50	100.00
		aes_alert_reset	18.000s	204.746us	50	50	100.00
V2	trigger_clear_test	aes_clear	38.000s	2.220ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	513.206us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	204.746us	50	50	100.00
V2	stress	aes_stress	18.000s	1.142ms	50	50	100.00
V2	sideload	aes_stress	18.000s	1.142ms	50	50	100.00
		aes_sideload	51.000s	1.831ms	50	50	100.00
V2	deinitialization	aes_deinit	23.000s	851.976us	50	50	100.00
V2	stress_all	aes_stress_all	4.967m	17.556ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	53.241us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	210.649us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	210.649us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	18.000s	109.737us	5	5	100.00
		aes_csr_rw	9.000s	89.763us	20	20	100.00
		aes_csr_aliasing	6.083m	10.022ms	4	5	80.00
		aes_same_csr_outstanding	3.300m	10.027ms	18	20	90.00
V2	tl_d_partial_access	aes_csr_hw_reset	18.000s	109.737us	5	5	100.00
		aes_csr_rw	9.000s	89.763us	20	20	100.00
		aes_csr_aliasing	6.083m	10.022ms	4	5	80.00
		aes_same_csr_outstanding	3.300m	10.027ms	18	20	90.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	3.067m	6.037ms	50	50	100.00
V2S	fault_inject	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	70.648us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	3.751ms	5	5	100.00
		aes_tl_intg_err	13.000s	395.834us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	395.834us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	204.746us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	28.000s	1.454ms	50	50	100.00
		aes_stress	18.000s	1.142ms	50	50	100.00
		aes_alert_reset	18.000s	204.746us	50	50	100.00
		aes_core_fi	1.267m	10.013ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	194.099us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	189.253us	50	50	100.00
		aes_stress	18.000s	1.142ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	1.142ms	50	50	100.00
		aes_sideload	51.000s	1.831ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	189.253us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	189.253us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	189.253us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	189.253us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	189.253us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	1.142ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	1.142ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	21.000s	735.094us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	21.000s	735.094us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.018ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	21.000s	735.094us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	204.746us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_ctr_fi	19.000s	124.625us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	21.000s	735.094us	50	50	100.00
		aes_control_fi	46.000s	10.009ms	276	300	92.00
		aes_cipher_fi	51.000s	10.018ms	338	350	96.57
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.583m	26.235ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.52	98.89	97.25	99.37	95.90	97.72	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_control_fi has 18 failures.
  - 26.aes_control_fi.110415470745411038390233196577561411865084996532603993283128143956300562421001
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:9af66732-2af6-4e28-96d3-868c34d58bf6
```
  - 32.aes_control_fi.69379550975123954393887466356321032754923912487819068263757211008079671962423
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:82351c6f-6f9b-488c-b178-4a1b7502a2bc
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 5 failures.
  - 37.aes_cipher_fi.2013976775433501799008922083689704530140218861320891153363136367705595416159
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:eb706938-00d4-4784-b7d5-c07122ec3361
```
  - 98.aes_cipher_fi.95290113935962990788489232735446027520988243912003736197112896719998558121859
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/98.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1a4dff81-336c-42ef-875e-ac939fcd93a5
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 13.aes_cipher_fi.65637487496002064810212382784099570784590596767300811543398533286790478202433
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006554856 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006554856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.aes_cipher_fi.84085160709509557261783096328171976294751287121247795229460514110210614590959
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013967118 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013967118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 5.aes_control_fi.109208089319440916419741997584521725993424296637883655285809220715732608521913
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013081792 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013081792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_control_fi.55717150744573364503598701380067555560042365662181400229749563980560583884608
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008673542 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008673542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.65361247940221994739275594701643759982648798493557851085347363907853676360413
Line 1242, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 793813283 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 793813283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.78487120272858254894973923802797827406876411291375762958949884889305340104434
Line 1228, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2277989260 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2277989260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.66622954537755242573264339731591722679109061555127091670691673435238740821560
Line 713, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1096768717 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1096768717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.59121249142168686687791441064537657910505586088809577138719004003044124060239
Line 704, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29538585482 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 29538585482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_same_csr_outstanding has 2 failures.
  - 2.aes_same_csr_outstanding.63603767454853122566429233344889723666460630012807928282019170956994986931563
    Line 300, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10027182865 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x9cda6584) == 0x0
  UVM_INFO @ 10027182865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_same_csr_outstanding.67387387301501844029504791609056791194029622174705820148232615634868387622704
    Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10017691086 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x93960984) == 0x0
  UVM_INFO @ 10017691086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.12217120194248762996976568319856114014566379227708182764731916412575786036317
    Line 378, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 678638419 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 678638419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.13238538214839456063441699047879098215710368976295148100628242245807614688378
    Line 344, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234332911 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 234332911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 36.aes_core_fi.108917657464254632827638346963574542066600452367961612872351188580575812200974
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024090540 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024090540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_core_fi.11988139479256940725420986882964527111737267294948987551867491895097725026974
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013311476 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013311476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 0.aes_csr_aliasing.102093414679567757962842256668277343548821747780267515645518660924126424285183
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10022158994 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x2fa29e84) == 0x0
  UVM_INFO @ 10022158994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```