AES/MASKED Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	77.491us	1	1	100.00
V1	smoke	aes_smoke	34.000s	1.287ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	70.347us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	56.385us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	4.554ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	322.726us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	280.204us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	56.385us	20	20	100.00
		aes_csr_aliasing	6.000s	322.726us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	34.000s	1.287ms	50	50	100.00
		aes_config_error	23.000s	757.082us	50	50	100.00
		aes_stress	42.000s	1.220ms	50	50	100.00
V2	key_length	aes_smoke	34.000s	1.287ms	50	50	100.00
		aes_config_error	23.000s	757.082us	50	50	100.00
		aes_stress	42.000s	1.220ms	50	50	100.00
V2	back2back	aes_stress	42.000s	1.220ms	50	50	100.00
		aes_b2b	1.083m	939.169us	50	50	100.00
V2	backpressure	aes_stress	42.000s	1.220ms	50	50	100.00
V2	multi_message	aes_smoke	34.000s	1.287ms	50	50	100.00
		aes_config_error	23.000s	757.082us	50	50	100.00
		aes_stress	42.000s	1.220ms	50	50	100.00
		aes_alert_reset	28.000s	1.240ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	66.998us	50	50	100.00
		aes_config_error	23.000s	757.082us	50	50	100.00
		aes_alert_reset	28.000s	1.240ms	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	3.043ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	20.000s	735.552us	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	1.240ms	50	50	100.00
V2	stress	aes_stress	42.000s	1.220ms	50	50	100.00
V2	sideload	aes_stress	42.000s	1.220ms	50	50	100.00
		aes_sideload	15.000s	298.773us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	84.004us	50	50	100.00
V2	stress_all	aes_stress_all	3.667m	9.603ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	149.474us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	119.414us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	119.414us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	70.347us	5	5	100.00
		aes_csr_rw	7.000s	56.385us	20	20	100.00
		aes_csr_aliasing	6.000s	322.726us	5	5	100.00
		aes_same_csr_outstanding	7.000s	375.992us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	70.347us	5	5	100.00
		aes_csr_rw	7.000s	56.385us	20	20	100.00
		aes_csr_aliasing	6.000s	322.726us	5	5	100.00
		aes_same_csr_outstanding	7.000s	375.992us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	47.000s	1.497ms	50	50	100.00
V2S	fault_inject	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	284.264us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	846.509us	5	5	100.00
		aes_tl_intg_err	14.000s	2.335ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	2.335ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	1.240ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	34.000s	1.287ms	50	50	100.00
		aes_stress	42.000s	1.220ms	50	50	100.00
		aes_alert_reset	28.000s	1.240ms	50	50	100.00
		aes_core_fi	30.000s	10.010ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	116.233us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	135.631us	50	50	100.00
		aes_stress	42.000s	1.220ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	42.000s	1.220ms	50	50	100.00
		aes_sideload	15.000s	298.773us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	135.631us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	135.631us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	135.631us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	135.631us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	135.631us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	42.000s	1.220ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	42.000s	1.220ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	3.344ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	3.344ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.008ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	3.344ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	1.240ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_ctr_fi	14.000s	74.827us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	3.344ms	50	50	100.00
		aes_control_fi	18.000s	107.511us	285	300	95.00
		aes_cipher_fi	50.000s	10.008ms	340	350	97.14
V2S		TOTAL			959	985	97.36
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.883m	10.766ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1566	1602	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	98.92	97.29	99.43	95.84	97.64	97.78	99.11	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 12 failures.
  - 15.aes_control_fi.15372731744131807062750528288127630730319665152273558886798482760286840062099
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:58d98ebe-6d77-4ddc-88cd-11ab7a01c2b0
```
  - 32.aes_control_fi.21144135670939164955907686912008009145343153251073774955655550427547503352898
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:d103adc5-cd28-4cca-bb3d-6f45eda5193c
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 5 failures.
  - 52.aes_cipher_fi.88305581970311587802470626463316304013944072003467202625337729518991479654334
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ebe3b95d-dc40-47ca-8930-87057f7e93b0
```
  - 188.aes_cipher_fi.26204760296547643619373099566381305181660406132113105342271342523734321649808
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/188.aes_cipher_fi/latest/run.log
```
  Job ID: smart:16d6f4d9-13f7-4064-8f29-db4ad8420f40
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.43599342203031962878459683517824802737162704827661198443673258596853633854626
Line 594, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 707400148 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 707400148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.63214298649372213278637435720174363943365644232126879451073229147768622736715
Line 1337, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1628200704 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1628200704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 21.aes_cipher_fi.42323767058934380899405177555231142945925562200225284102497549992164884630131
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009398429 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009398429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 275.aes_cipher_fi.4146930111693594616530676088816294591810530097928372436212670598883500079700
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/275.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007867640 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007867640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 1.aes_control_fi.84189930230290752273703633496261113420274023990143555160591376999141811239550
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026185858 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026185858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_control_fi.114937568339826544183405381402124744606010767440500817011434630841355582796899
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10054830688 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10054830688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 0.aes_core_fi.23131382365017114267186891187212023639586371897950934565549449876655483516424
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010263760 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010263760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.7571810726531013112166738917466207036192504609611722292429012218598362006988
    Line 503, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 259271473 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 259271473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.62295795258315873765555355092066906377048434372359189671026305180435150817424
    Line 348, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1463206803 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1463206803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```