AES/MASKED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	66.303us	1	1	100.00
V1	smoke	aes_smoke	12.000s	402.980us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	77.827us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	69.830us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.103ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	456.268us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	328.938us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	69.830us	20	20	100.00
		aes_csr_aliasing	5.000s	456.268us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	402.980us	50	50	100.00
		aes_config_error	34.000s	1.106ms	50	50	100.00
		aes_stress	1.150m	2.189ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	402.980us	50	50	100.00
		aes_config_error	34.000s	1.106ms	50	50	100.00
		aes_stress	1.150m	2.189ms	50	50	100.00
V2	back2back	aes_stress	1.150m	2.189ms	50	50	100.00
		aes_b2b	2.150m	1.548ms	50	50	100.00
V2	backpressure	aes_stress	1.150m	2.189ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	402.980us	50	50	100.00
		aes_config_error	34.000s	1.106ms	50	50	100.00
		aes_stress	1.150m	2.189ms	50	50	100.00
		aes_alert_reset	1.950m	5.798ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	78.961us	50	50	100.00
		aes_config_error	34.000s	1.106ms	50	50	100.00
		aes_alert_reset	1.950m	5.798ms	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	722.171us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	28.000s	811.969us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.950m	5.798ms	50	50	100.00
V2	stress	aes_stress	1.150m	2.189ms	50	50	100.00
V2	sideload	aes_stress	1.150m	2.189ms	50	50	100.00
		aes_sideload	17.000s	2.193ms	50	50	100.00
V2	deinitialization	aes_deinit	45.000s	1.487ms	50	50	100.00
V2	stress_all	aes_stress_all	5.500m	11.079ms	10	10	100.00
V2	alert_test	aes_alert_test	11.000s	109.455us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	92.792us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	92.792us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	77.827us	5	5	100.00
		aes_csr_rw	3.000s	69.830us	20	20	100.00
		aes_csr_aliasing	5.000s	456.268us	5	5	100.00
		aes_same_csr_outstanding	4.000s	144.149us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	77.827us	5	5	100.00
		aes_csr_rw	3.000s	69.830us	20	20	100.00
		aes_csr_aliasing	5.000s	456.268us	5	5	100.00
		aes_same_csr_outstanding	4.000s	144.149us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	30.000s	720.402us	49	50	98.00
V2S	fault_inject	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	128.342us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	1.149ms	5	5	100.00
		aes_tl_intg_err	5.000s	258.646us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	258.646us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.950m	5.798ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	402.980us	50	50	100.00
		aes_stress	1.150m	2.189ms	50	50	100.00
		aes_alert_reset	1.950m	5.798ms	50	50	100.00
		aes_core_fi	1.450m	10.004ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	75.300us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	57.367us	50	50	100.00
		aes_stress	1.150m	2.189ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.150m	2.189ms	50	50	100.00
		aes_sideload	17.000s	2.193ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	57.367us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	57.367us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	57.367us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	57.367us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	57.367us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.150m	2.189ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.150m	2.189ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	403.622us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	403.622us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.031ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	403.622us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.950m	5.798ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_ctr_fi	11.000s	81.473us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	403.622us	50	50	100.00
		aes_control_fi	48.000s	10.012ms	286	300	95.33
		aes_cipher_fi	32.000s	10.031ms	337	350	96.29
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.383m	2.864ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.55	96.32	99.43	95.83	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 8 failures.
  - 31.aes_control_fi.86509090092301241104661911797515175272060127541181724558957730419547375607331
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job ID: smart:b30466c8-a259-42d4-8014-87727c2434bf
```
  - 55.aes_control_fi.64640108292683018482363428190921767235351255958597455930950292047309204822984
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:f4146525-8d06-4802-b5e2-aa6bd400e8f3
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 8 failures.
  - 89.aes_cipher_fi.25126168781622919265291420293305671363118298108362137157416457819890326957855
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bd471f9f-517f-4af6-a64e-e131b9b62b84
```
  - 116.aes_cipher_fi.88678496803825765995508196420438770623914270156272824778169097558623375594615
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/116.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7319fafa-aada-43d1-80cc-7e2874ffc8a9
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.9477564118206727591887354789379358921671583606800897822235535282143632242134
Line 576, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10560755921 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10560755921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.108218190572660288815771295644695785910172175958062886031410549831847241283592
Line 578, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 691970282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 691970282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 16.aes_control_fi.80503375636155665666963660615210739858840379731006929626252502721774418276427
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012087420 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012087420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_control_fi.73043451897547311156349821828406752261228514782062909855240661980623286720248
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012288499 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012288499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 2.aes_cipher_fi.46366415182660173413861214149755251798251810041863415304000292628965071823132
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012858507 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012858507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_cipher_fi.32330376619113856612729681491719585782485585725636713727645732227432045111958
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028987307 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028987307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 21.aes_core_fi.98513350636856081559057401984500425965770485941997777451180956372559449244829
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003628293 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003628293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_core_fi.108478047598132597931978784377164758074115732927965529921050333846823073150588
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018947920 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018947920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.53021549448023936302218770260312694087426248899282846660211204374320848403336
Line 1149, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2161390502 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2161390502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.73493045290162189440555056664554316986654772587971104647643855912003574310060
Line 1342, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2863590517 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2863590517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.10207357102857444394705162447025890258667900647711669482283219572960380434371
    Line 396, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  59552816 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  59552816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 46.aes_reseed.62396957753242804646927096576585453605856186001003003347917038802355314296013
    Line 2935, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_reseed/latest/run.log
```
  UVM_FATAL @ 155749897 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 155749897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```