AES/MASKED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	106.865us	1	1	100.00
V1	smoke	aes_smoke	14.000s	66.023us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	54.052us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	87.946us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	178.599us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	181.586us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	139.951us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	87.946us	20	20	100.00
		aes_csr_aliasing	5.000s	181.586us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	66.023us	50	50	100.00
		aes_config_error	14.000s	149.577us	50	50	100.00
		aes_stress	1.033m	2.168ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	66.023us	50	50	100.00
		aes_config_error	14.000s	149.577us	50	50	100.00
		aes_stress	1.033m	2.168ms	50	50	100.00
V2	back2back	aes_stress	1.033m	2.168ms	50	50	100.00
		aes_b2b	34.000s	379.139us	50	50	100.00
V2	backpressure	aes_stress	1.033m	2.168ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	66.023us	50	50	100.00
		aes_config_error	14.000s	149.577us	50	50	100.00
		aes_stress	1.033m	2.168ms	50	50	100.00
		aes_alert_reset	31.000s	1.017ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	19.000s	65.659us	50	50	100.00
		aes_config_error	14.000s	149.577us	50	50	100.00
		aes_alert_reset	31.000s	1.017ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.917m	6.334ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	42.000s	1.752ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	31.000s	1.017ms	50	50	100.00
V2	stress	aes_stress	1.033m	2.168ms	50	50	100.00
V2	sideload	aes_stress	1.033m	2.168ms	50	50	100.00
		aes_sideload	15.000s	119.487us	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	132.506us	50	50	100.00
V2	stress_all	aes_stress_all	2.050m	8.575ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	50.655us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	125.601us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	125.601us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	54.052us	5	5	100.00
		aes_csr_rw	7.000s	87.946us	20	20	100.00
		aes_csr_aliasing	5.000s	181.586us	5	5	100.00
		aes_same_csr_outstanding	8.000s	93.100us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	54.052us	5	5	100.00
		aes_csr_rw	7.000s	87.946us	20	20	100.00
		aes_csr_aliasing	5.000s	181.586us	5	5	100.00
		aes_same_csr_outstanding	8.000s	93.100us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	22.000s	1.207ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	118.700us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	19.000s	643.808us	5	5	100.00
		aes_tl_intg_err	7.000s	271.314us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	271.314us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	31.000s	1.017ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	66.023us	50	50	100.00
		aes_stress	1.033m	2.168ms	50	50	100.00
		aes_alert_reset	31.000s	1.017ms	50	50	100.00
		aes_core_fi	45.000s	10.018ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	96.395us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	102.745us	50	50	100.00
		aes_stress	1.033m	2.168ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.033m	2.168ms	50	50	100.00
		aes_sideload	15.000s	119.487us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	102.745us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	102.745us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	102.745us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	102.745us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	102.745us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.033m	2.168ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.033m	2.168ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	412.497us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	412.497us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.057ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	412.497us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	31.000s	1.017ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_ctr_fi	13.000s	83.853us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	412.497us	50	50	100.00
		aes_control_fi	49.000s	10.007ms	285	300	95.00
		aes_cipher_fi	42.000s	10.057ms	342	350	97.71
V2S		TOTAL			961	985	97.56
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.100m	10.686ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1567	1602	97.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.55	96.32	99.45	95.89	97.72	100.00	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test aes_control_fi has 9 failures.
  - 20.aes_control_fi.77147492772533423963519062045281707682623856229601983627030910449693107634782
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:f6d1c16e-2c9a-451d-a4ab-a8f098ed7501
```
  - 76.aes_control_fi.15085031122491717500469413955443618947536037215672992973171884075761085034907
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/76.aes_control_fi/latest/run.log
```
  Job ID: smart:ee2ada2e-6f2f-4fa6-bc5c-b10090741ef5
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 3 failures.
  - 162.aes_cipher_fi.2818270341529483375817822480430877176157247198983031586407254524826652433018
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/162.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0436a473-18b7-467e-960e-eb678823e1e8
```
  - 244.aes_cipher_fi.62345219378313366968849459125183316608614169369967093307037286198102725444760
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/244.aes_cipher_fi/latest/run.log
```
  Job ID: smart:09bd1fe5-29ac-48d2-866e-dc4041d3a2d3
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 54.aes_control_fi.52662667374164909780243189713172447793053028743700980766189718899522518049905
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015581548 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015581548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.aes_control_fi.26594695302123537632061436308167982294249742802277476199394610428709518454534
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006737088 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006737088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 143.aes_cipher_fi.49101059650920063631541781087093804151380912607207599849749056823981751935893
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/143.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10185811985 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10185811985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 175.aes_cipher_fi.51171340156300373944792267224435209522074370077703900073819787465042292275177
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/175.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020948869 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020948869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.98119488074974051722069718860313157346596903451067789380244454618422553698236
Line 1242, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1321509404 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1321509404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.85425664565749043054691890945740796709168197058828925050992359880691060587555
Line 994, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1185332637 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1185332637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.67588797776306734231392795849189624411892593370245759550889932733210840980952
Line 1702, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 941603687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 941603687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.101520996763031418138169640681184761702639890040477925706779424323774010757063
Line 1234, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4096726563 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4096726563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.115759797817119575520471840065450520242058570744409378196861085301361192930888
    Line 1847, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10686254842 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10686254842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.aes_csr_mem_rw_with_rand_reset.106253719092112862562157037437455240826281649221226554127799088425541567096253
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 341885798 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 341885798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.47725760727007262224178017998077353884210232566617319353417748741506726497144
    Line 937, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6994133004 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6994133004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.109871512331973138836403356773482402825144786301279600434205004628747336268682
    Line 455, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 531313913 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 531313913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.7701719559965297295621819258967240064664563494872678292322768658201301034132
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018171656 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018171656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```