AES/MASKED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	119.818us	1	1	100.00
V1	smoke	aes_smoke	18.000s	100.349us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	84.144us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.750m	10.014ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	620.233us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	14.000s	142.992us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	16.000s	128.210us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.750m	10.014ms	19	20	95.00
		aes_csr_aliasing	14.000s	142.992us	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	18.000s	100.349us	50	50	100.00
		aes_config_error	1.267m	2.387ms	50	50	100.00
		aes_stress	18.000s	1.188ms	50	50	100.00
V2	key_length	aes_smoke	18.000s	100.349us	50	50	100.00
		aes_config_error	1.267m	2.387ms	50	50	100.00
		aes_stress	18.000s	1.188ms	50	50	100.00
V2	back2back	aes_stress	18.000s	1.188ms	50	50	100.00
		aes_b2b	44.000s	485.242us	50	50	100.00
V2	backpressure	aes_stress	18.000s	1.188ms	50	50	100.00
V2	multi_message	aes_smoke	18.000s	100.349us	50	50	100.00
		aes_config_error	1.267m	2.387ms	50	50	100.00
		aes_stress	18.000s	1.188ms	50	50	100.00
		aes_alert_reset	23.000s	817.617us	50	50	100.00
V2	failure_test	aes_man_cfg_err	15.000s	53.786us	50	50	100.00
		aes_config_error	1.267m	2.387ms	50	50	100.00
		aes_alert_reset	23.000s	817.617us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.800m	4.342ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	548.777us	1	1	100.00
V2	reset_recovery	aes_alert_reset	23.000s	817.617us	50	50	100.00
V2	stress	aes_stress	18.000s	1.188ms	50	50	100.00
V2	sideload	aes_stress	18.000s	1.188ms	50	50	100.00
		aes_sideload	23.000s	4.543ms	50	50	100.00
V2	deinitialization	aes_deinit	52.000s	1.555ms	50	50	100.00
V2	stress_all	aes_stress_all	1.267m	1.065ms	10	10	100.00
V2	alert_test	aes_alert_test	19.000s	52.090us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	116.789us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	116.789us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	84.144us	5	5	100.00
		aes_csr_rw	1.750m	10.014ms	19	20	95.00
		aes_csr_aliasing	14.000s	142.992us	5	5	100.00
		aes_same_csr_outstanding	19.000s	297.863us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	84.144us	5	5	100.00
		aes_csr_rw	1.750m	10.014ms	19	20	95.00
		aes_csr_aliasing	14.000s	142.992us	5	5	100.00
		aes_same_csr_outstanding	19.000s	297.863us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	22.000s	82.703us	50	50	100.00
V2S	fault_inject	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	164.576us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	470.539us	5	5	100.00
		aes_tl_intg_err	15.000s	357.989us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	357.989us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	23.000s	817.617us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	100.349us	50	50	100.00
		aes_stress	18.000s	1.188ms	50	50	100.00
		aes_alert_reset	23.000s	817.617us	50	50	100.00
		aes_core_fi	35.000s	1.800ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	116.109us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	53.125us	50	50	100.00
		aes_stress	18.000s	1.188ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	1.188ms	50	50	100.00
		aes_sideload	23.000s	4.543ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	53.125us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	53.125us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	53.125us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	53.125us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	53.125us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	1.188ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	1.188ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	1.744ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	1.744ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.029ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	1.744ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	23.000s	817.617us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_ctr_fi	14.000s	97.162us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	1.744ms	49	50	98.00
		aes_control_fi	51.000s	10.147ms	285	300	95.00
		aes_cipher_fi	46.000s	10.029ms	338	350	96.57
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.317m	10.687ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.44	95.67	97.72	97.78	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test aes_control_fi has 9 failures.
  - 134.aes_control_fi.32280228099487698013173334487456824747405267963715848058786705878245215070442
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/134.aes_control_fi/latest/run.log
```
  Job ID: smart:dc79c10d-b0a2-40c0-81f1-da7a9bc6fb60
```
  - 179.aes_control_fi.60704352219062120015938706640955060302488262557402293942209880449502310083690
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/179.aes_control_fi/latest/run.log
```
  Job ID: smart:089dd42f-1187-4a41-95a0-44045ea510ec
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 4 failures.
  - 156.aes_cipher_fi.72433424593738770542075939728157033567523550097485008883546936768702497368796
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/156.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0902a5e0-12d3-4a5e-ae00-249f29072948
```
  - 189.aes_cipher_fi.68825000766697598197266063896120688266398129297102385050157686407174024130909
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/189.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9b3ca9ef-f102-494f-8b17-9dfe0fb4a333
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 42.aes_cipher_fi.58931167907963888026473793783797827252946759783064180642965553898664587423771
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029337298 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029337298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.112785820786795868703489132328754427991368912643214815690391278709088577528267
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010491964 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010491964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.76676934926292313725475983438326051052964302878719786989262204034245462934101
Line 1332, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4315128340 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4315128340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.64655615958520856930129273375168069491551705655998477494675873231080898958444
Line 787, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2220955021 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2220955021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 114.aes_control_fi.71823282386872644957964840080134871726205780019172633686223690474203013198322
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013947959 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013947959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 135.aes_control_fi.94205976693836811706637667550615011933168048004154421545784955034242873922537
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/135.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016101558 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016101558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.34725254472386161808174667112859335763621923482184995366792448307905222176737
Line 1073, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 491336425 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 491336425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.45608685390463420321996132241553468195328906784845578761514531341415612523847
Line 1859, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10687079852 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10687079852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 25.aes_core_fi.93412068130189055465639071780765707639173666551604441767575993166722023212061
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032088056 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032088056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.9480853673206947719057753340369419296997440114650227771630012245338158996691
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009267423 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009267423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.aes_csr_mem_rw_with_rand_reset.41101538751457797734727473285019993670892686107372289552014430198748231819366
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 128210486 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 128210486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.62726396993896853346550184111172257532729951788642466069098170941509763516022
    Line 486, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 368192837 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 368192837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 19.aes_csr_rw.19132496981280515498716951633462066875490781917252293354463913248835621641315
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10014495830 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x4ea2a784) == 0x0
  UVM_INFO @ 10014495830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 28.aes_fi.39951650300015197364153706542480339420887602198609462306320362509618969214741
    Line 36291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_fi/latest/run.log
```
  UVM_FATAL @ 330507303 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 330507303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```