AES/MASKED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	61.599us	1	1	100.00
V1	smoke	aes_smoke	15.000s	62.607us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	71.806us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	51.466us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	182.873us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	160.138us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	92.434us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	51.466us	20	20	100.00
		aes_csr_aliasing	5.000s	160.138us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	62.607us	50	50	100.00
		aes_config_error	22.000s	1.261ms	50	50	100.00
		aes_stress	2.433m	3.709ms	50	50	100.00
V2	key_length	aes_smoke	15.000s	62.607us	50	50	100.00
		aes_config_error	22.000s	1.261ms	50	50	100.00
		aes_stress	2.433m	3.709ms	50	50	100.00
V2	back2back	aes_stress	2.433m	3.709ms	50	50	100.00
		aes_b2b	35.000s	1.229ms	50	50	100.00
V2	backpressure	aes_stress	2.433m	3.709ms	50	50	100.00
V2	multi_message	aes_smoke	15.000s	62.607us	50	50	100.00
		aes_config_error	22.000s	1.261ms	50	50	100.00
		aes_stress	2.433m	3.709ms	50	50	100.00
		aes_alert_reset	11.000s	89.002us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	123.089us	50	50	100.00
		aes_config_error	22.000s	1.261ms	50	50	100.00
		aes_alert_reset	11.000s	89.002us	50	50	100.00
V2	trigger_clear_test	aes_clear	22.000s	1.232ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	206.296us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	89.002us	50	50	100.00
V2	stress	aes_stress	2.433m	3.709ms	50	50	100.00
V2	sideload	aes_stress	2.433m	3.709ms	50	50	100.00
		aes_sideload	15.000s	849.379us	50	50	100.00
V2	deinitialization	aes_deinit	49.000s	3.233ms	50	50	100.00
V2	stress_all	aes_stress_all	3.050m	5.605ms	9	10	90.00
V2	alert_test	aes_alert_test	9.000s	56.698us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	332.555us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	332.555us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	71.806us	5	5	100.00
		aes_csr_rw	3.000s	51.466us	20	20	100.00
		aes_csr_aliasing	5.000s	160.138us	5	5	100.00
		aes_same_csr_outstanding	5.000s	120.463us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	71.806us	5	5	100.00
		aes_csr_rw	3.000s	51.466us	20	20	100.00
		aes_csr_aliasing	5.000s	160.138us	5	5	100.00
		aes_same_csr_outstanding	5.000s	120.463us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	31.000s	1.610ms	50	50	100.00
V2S	fault_inject	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.117m	10.021ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	8.000s	683.498us	5	5	100.00
		aes_tl_intg_err	5.000s	159.494us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	159.494us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	89.002us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	62.607us	50	50	100.00
		aes_stress	2.433m	3.709ms	50	50	100.00
		aes_alert_reset	11.000s	89.002us	50	50	100.00
		aes_core_fi	1.417m	10.006ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	70.381us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	100.264us	50	50	100.00
		aes_stress	2.433m	3.709ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.433m	3.709ms	50	50	100.00
		aes_sideload	15.000s	849.379us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	100.264us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	100.264us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	100.264us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	100.264us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	100.264us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.433m	3.709ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.433m	3.709ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	20.000s	710.691us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	20.000s	710.691us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.004ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	20.000s	710.691us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	89.002us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_ctr_fi	13.000s	85.229us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	20.000s	710.691us	50	50	100.00
		aes_control_fi	42.000s	10.009ms	279	300	93.00
		aes_cipher_fi	49.000s	10.004ms	336	350	96.00
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.833m	31.678ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.57	96.37	99.45	95.85	97.64	100.00	98.96	96.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 15 failures.
  - 13.aes_control_fi.111177783302324362248869560671727839962549686311365783744893928540450859040294
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:44e4c5d7-5cc4-4a15-8bb0-52bf3bd35865
```
  - 18.aes_control_fi.103211852996044664364990282010074540059683260559259609882857035607616560191634
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:a89dec3a-c6e5-49cd-974b-d48924b4de52
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 7 failures.
  - 73.aes_cipher_fi.92993509770987205425647768779977172251445445656048282345215370929765410736163
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c78bc867-c587-4ca2-891c-1c364e836759
```
  - 188.aes_cipher_fi.86119015992512553312951152048776394827816942214958820962515803545517379945593
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/188.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cc4d41de-cf31-4d4e-a847-0f0beb7d6377
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.18332931214130217609670667677049357618140554398733597821052405902750915352938
Line 1359, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1387620829 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1387620829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.94600773571342651598438510702568646381622143653710130042808522704425223072177
Line 800, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31678457284 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 31678457284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 32.aes_cipher_fi.20775007682074038030008116986250997942733428738940336670517559392136247102265
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004657670 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004657670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 121.aes_cipher_fi.44625578375234203684940504315191586374802812623821581998581705857975345895577
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/121.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012431933 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012431933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 1.aes_control_fi.16868933407034939194150822965442012569104512984913516671923356818457060425573
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007761734 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007761734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_control_fi.50364196868510432835306632835613086002802073428579633113668082829962662180776
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020517517 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020517517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 33.aes_core_fi.86185958779018337696755203752110724032389408273118031550593897521748657944138
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006201877 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006201877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_core_fi.76452237864493815432242949547840874655779307659852415577327836518981119176139
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008514294 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008514294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.77963422556449594352330545218678777712471833814296231394036457582150043034544
    Line 499, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 471836170 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 471836170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.86318276055226391223664658750287753648531528608514396416611228550359309687181
    Line 51521, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 281193284 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 281172876 PS)
  UVM_ERROR @ 281193284 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 281193284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.aes_shadow_reg_errors_with_csr_rw.19167547051064124521234738800711173054332387070802735085930033059687697688433
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10021261534 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x702b084) == 0x0
  UVM_INFO @ 10021261534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```