AES/MASKED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.283us	1	1	100.00
V1	smoke	aes_smoke	13.000s	301.883us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	63.293us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	124.463us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	23.000s	520.274us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	161.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	86.169us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	124.463us	20	20	100.00
		aes_csr_aliasing	5.000s	161.899us	5	5	100.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	13.000s	301.883us	50	50	100.00
		aes_config_error	41.000s	1.059ms	50	50	100.00
		aes_stress	11.000s	976.766us	50	50	100.00
V2	key_length	aes_smoke	13.000s	301.883us	50	50	100.00
		aes_config_error	41.000s	1.059ms	50	50	100.00
		aes_stress	11.000s	976.766us	50	50	100.00
V2	back2back	aes_stress	11.000s	976.766us	50	50	100.00
		aes_b2b	47.000s	564.990us	50	50	100.00
V2	backpressure	aes_stress	11.000s	976.766us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	301.883us	50	50	100.00
		aes_config_error	41.000s	1.059ms	50	50	100.00
		aes_stress	11.000s	976.766us	50	50	100.00
		aes_alert_reset	13.000s	2.837ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	55.324us	50	50	100.00
		aes_config_error	41.000s	1.059ms	50	50	100.00
		aes_alert_reset	13.000s	2.837ms	50	50	100.00
V2	trigger_clear_test	aes_clear	29.000s	1.544ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.530ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	2.837ms	50	50	100.00
V2	stress	aes_stress	11.000s	976.766us	50	50	100.00
V2	sideload	aes_stress	11.000s	976.766us	50	50	100.00
		aes_sideload	14.000s	413.759us	50	50	100.00
V2	deinitialization	aes_deinit	1.450m	2.540ms	50	50	100.00
V2	stress_all	aes_stress_all	2.550m	8.486ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	155.877us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	136.491us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	136.491us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	63.293us	5	5	100.00
		aes_csr_rw	5.000s	124.463us	20	20	100.00
		aes_csr_aliasing	5.000s	161.899us	5	5	100.00
		aes_same_csr_outstanding	6.000s	186.608us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	63.293us	5	5	100.00
		aes_csr_rw	5.000s	124.463us	20	20	100.00
		aes_csr_aliasing	5.000s	161.899us	5	5	100.00
		aes_same_csr_outstanding	6.000s	186.608us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	26.000s	3.935ms	47	50	94.00
V2S	fault_inject	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	297.233us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	3.141ms	5	5	100.00
		aes_tl_intg_err	9.000s	2.003ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	2.003ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	2.837ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	301.883us	50	50	100.00
		aes_stress	11.000s	976.766us	50	50	100.00
		aes_alert_reset	13.000s	2.837ms	50	50	100.00
		aes_core_fi	1.317m	10.011ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	146.325us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	88.327us	50	50	100.00
		aes_stress	11.000s	976.766us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	976.766us	50	50	100.00
		aes_sideload	14.000s	413.759us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	88.327us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	88.327us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	88.327us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	88.327us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	88.327us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	976.766us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	976.766us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.217m	2.629ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.217m	2.629ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.217m	2.629ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	2.837ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_ctr_fi	12.000s	477.554us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.217m	2.629ms	49	50	98.00
		aes_control_fi	49.000s	10.007ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	337	350	96.29
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.350m	8.998ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.53	96.25	99.42	95.78	97.72	97.78	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 15 failures.
  - 2.aes_control_fi.69254524682421853213374419655526279763023294387571755378726142136551753463813
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job ID: smart:14054c7b-43a4-4fa9-8b8c-c1418662da28
```
  - 34.aes_control_fi.86599417094079158398869620793193845866738071043782961570238668241418113890738
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:2dfd6492-d43f-41c7-b331-de3b05dea983
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 81.aes_cipher_fi.54252989647728770003656856531318202436199985572615224976283719708532506202824
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/81.aes_cipher_fi/latest/run.log
```
  Job ID: smart:69ebecaf-5d4e-4e63-8a25-5875d6823350
```
  - 91.aes_cipher_fi.108708829332541643042772285688710077887344957605693435221898966116892865402807
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/91.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9477c560-aaec-4afb-a87d-0f8ff25f4741
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 89.aes_cipher_fi.99475339446658078738117169087114437348977325801194395399825219596706806649371
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10236521263 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10236521263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 111.aes_cipher_fi.23202021786195580271880577764105564145148248020785667501199936419567798971115
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/111.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026477764 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026477764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.62940435494859880558005173973273124531444378698997590652137670375377452512467
Line 1564, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2986386114 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2986386114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.90625533197188887456610789699181598509285577985543269403256711111183865596503
Line 436, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8997888999 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8997888999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 20.aes_control_fi.9989012930960801637394432671453471917906385040032820306861682127271406323379
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006609524 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006609524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_control_fi.33672014798092909506488608973778850773245796887611490691227462963281182880371
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10029606287 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029606287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.39158092343372920991780186334174831180851064306598324804919030171763725987431
Line 1215, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2560285439 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2560285439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.2423152079077793910042760001145968055123686327477189155344293110766998954927
Line 1167, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 911089862 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 911089862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_csr_mem_rw_with_rand_reset has 2 failures.
  - 0.aes_csr_mem_rw_with_rand_reset.46859394962596721043896829051919275692297163301793597069063482895018009117412
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 511287428 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 511287428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_csr_mem_rw_with_rand_reset.74832487131841515271132695281698503248750694808237955357004076248775787208392
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 948162888 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 948162888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:

Test aes_reseed has 2 failures.

15.aes_reseed.39042516152035088527503349831053957053905756862479730100536013585601051060118
Line 822, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_reseed/latest/run.log

  UVM_FATAL @ 271505981 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 271505981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.aes_reseed.29253742005220472788378988847064891707858266727077432926807394650051478018266
Line 4302, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_reseed/latest/run.log

  UVM_FATAL @ 163186123 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 163186123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 21.aes_core_fi.113699831875147517510828081742044663458881858225741397398223178318393722625132
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007796687 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007796687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_core_fi.15836617936311673632385046654813828814230439677725222717296658219335914092066
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011468799 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011468799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 6.aes_fi.31508161120352074895040428269524556638231066661389369064680694844449865947500
    Line 2459, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 34742902 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 34732902 PS)
  UVM_ERROR @  34742902 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  34742902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 39.aes_reseed.34779730126564151683824897057408381846829544026422964336431493688925452559881
    Line 1955, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_reseed/latest/run.log
```
  UVM_FATAL @ 163585666 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 163585666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```