AES/MASKED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	80.266us	1	1	100.00
V1	smoke	aes_smoke	14.000s	114.370us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	53.020us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	69.633us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.889ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.039ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	425.416us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	69.633us	20	20	100.00
		aes_csr_aliasing	5.000s	1.039ms	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	114.370us	50	50	100.00
		aes_config_error	49.000s	1.895ms	50	50	100.00
		aes_stress	1.783m	3.257ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	114.370us	50	50	100.00
		aes_config_error	49.000s	1.895ms	50	50	100.00
		aes_stress	1.783m	3.257ms	50	50	100.00
V2	back2back	aes_stress	1.783m	3.257ms	50	50	100.00
		aes_b2b	1.200m	894.182us	50	50	100.00
V2	backpressure	aes_stress	1.783m	3.257ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	114.370us	50	50	100.00
		aes_config_error	49.000s	1.895ms	50	50	100.00
		aes_stress	1.783m	3.257ms	50	50	100.00
		aes_alert_reset	20.000s	1.394ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	23.000s	79.960us	50	50	100.00
		aes_config_error	49.000s	1.895ms	50	50	100.00
		aes_alert_reset	20.000s	1.394ms	50	50	100.00
V2	trigger_clear_test	aes_clear	23.000s	724.523us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.115ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	1.394ms	50	50	100.00
V2	stress	aes_stress	1.783m	3.257ms	50	50	100.00
V2	sideload	aes_stress	1.783m	3.257ms	50	50	100.00
		aes_sideload	1.500m	2.456ms	50	50	100.00
V2	deinitialization	aes_deinit	41.000s	5.783ms	50	50	100.00
V2	stress_all	aes_stress_all	1.100m	994.859us	10	10	100.00
V2	alert_test	aes_alert_test	19.000s	54.846us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	75.852us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	75.852us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	53.020us	5	5	100.00
		aes_csr_rw	3.000s	69.633us	20	20	100.00
		aes_csr_aliasing	5.000s	1.039ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	174.689us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	53.020us	5	5	100.00
		aes_csr_rw	3.000s	69.633us	20	20	100.00
		aes_csr_aliasing	5.000s	1.039ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	174.689us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	27.000s	133.564us	50	50	100.00
V2S	fault_inject	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	190.239us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	569.529us	5	5	100.00
		aes_tl_intg_err	6.000s	1.380ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.380ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	1.394ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	114.370us	50	50	100.00
		aes_stress	1.783m	3.257ms	50	50	100.00
		aes_alert_reset	20.000s	1.394ms	50	50	100.00
		aes_core_fi	33.000s	10.013ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	279.300us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	16.000s	85.233us	50	50	100.00
		aes_stress	1.783m	3.257ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.783m	3.257ms	50	50	100.00
		aes_sideload	1.500m	2.456ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	16.000s	85.233us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	16.000s	85.233us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	16.000s	85.233us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	16.000s	85.233us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	16.000s	85.233us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.783m	3.257ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.783m	3.257ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.433m	2.953ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.433m	2.953ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.012ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.433m	2.953ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	1.394ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_ctr_fi	14.000s	117.199us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.433m	2.953ms	50	50	100.00
		aes_control_fi	33.000s	10.014ms	286	300	95.33
		aes_cipher_fi	52.000s	10.012ms	334	350	95.43
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.633m	14.959ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.54	96.28	99.42	95.67	97.72	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 11 failures.
  - 10.aes_control_fi.38226331706422073879131005686004981615230764786470677655618502994123155945954
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:f591eeba-dd59-462e-9645-a486a99f6194
```
  - 39.aes_control_fi.80274340695727531741334476434318142303070602089358896243466331250913196315686
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:bbb3e2bd-0f35-4196-ae52-2641972ab9cb
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 7 failures.
  - 79.aes_cipher_fi.112183282484247781544228397748129562540585944452369109098703690383748241433823
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9945f76b-6167-46e4-ad34-09f4f2de8c01
```
  - 81.aes_cipher_fi.83295997860682144531279645562473677034417834936730403470250443519957474334289
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/81.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a1bec589-9be5-4cfa-9a9b-22f29360ccb2
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 46.aes_cipher_fi.4665203315506853317804186907719440642410526454058848667609923390389459959744
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010874414 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010874414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.57008823493675305192036062961479614321879577831761429603612901458141062135528
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019215957 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019215957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.102615570383461212317845065343234538190611395977383167365479306937769785832923
Line 743, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1133541856 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1133541856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.101432925181228767842207586519037207095130231830240128340394325789186155142335
Line 729, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13850134008 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 13850134008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.45171390376383339573683806857421980353055980310873117308692835860772142513687
    Line 1407, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2123372973 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2123372973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.37114692037972094959282786325172060803742734925307264605270815030183377809433
    Line 706, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3298091309 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3298091309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.aes_csr_mem_rw_with_rand_reset.26461178317411027320310780602036406548362904062463722968973240879349692034344
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 425416073 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 425416073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 5.aes_control_fi.63543580083585911869936781997390859354829978532766084669823792211251392178338
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011454417 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011454417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 109.aes_control_fi.67929335394391515153478868041227438674084272820101944170642197361630439679408
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/109.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019937366 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019937366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.17580829543707720133486749263442551043268421096573302726515712596469372866346
    Line 613, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1684246240 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1684246240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.45405835697920809896178874877752202060584269537499867106331266838724924367593
    Line 764, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6623942221 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6623942221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 21.aes_core_fi.14485527055650816148755780578823847918893764313138547760570242846419554073554
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015750184 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015750184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_core_fi.39921225984153099035772626710158014088649637486361428985115513834437253574468
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013390500 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013390500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.109706223476860965482333199237678665809520273892192527237257160801952759743956
    Line 642, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 451249826 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 451249826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```