AES/MASKED Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	91.377us	1	1	100.00
V1	smoke	aes_smoke	13.000s	185.829us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	132.055us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	74.767us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	512.229us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	123.437us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	14.000s	65.653us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	74.767us	20	20	100.00
		aes_csr_aliasing	5.000s	123.437us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	185.829us	50	50	100.00
		aes_config_error	15.000s	76.320us	50	50	100.00
		aes_stress	35.000s	2.934ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	185.829us	50	50	100.00
		aes_config_error	15.000s	76.320us	50	50	100.00
		aes_stress	35.000s	2.934ms	50	50	100.00
V2	back2back	aes_stress	35.000s	2.934ms	50	50	100.00
		aes_b2b	41.000s	488.069us	50	50	100.00
V2	backpressure	aes_stress	35.000s	2.934ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	185.829us	50	50	100.00
		aes_config_error	15.000s	76.320us	50	50	100.00
		aes_stress	35.000s	2.934ms	50	50	100.00
		aes_alert_reset	28.000s	1.929ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	116.191us	50	50	100.00
		aes_config_error	15.000s	76.320us	50	50	100.00
		aes_alert_reset	28.000s	1.929ms	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	590.281us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	248.282us	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	1.929ms	50	50	100.00
V2	stress	aes_stress	35.000s	2.934ms	50	50	100.00
V2	sideload	aes_stress	35.000s	2.934ms	50	50	100.00
		aes_sideload	20.000s	231.934us	50	50	100.00
V2	deinitialization	aes_deinit	20.000s	577.713us	50	50	100.00
V2	stress_all	aes_stress_all	10.183m	36.330ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	53.969us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	161.404us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	161.404us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	132.055us	5	5	100.00
		aes_csr_rw	13.000s	74.767us	20	20	100.00
		aes_csr_aliasing	5.000s	123.437us	5	5	100.00
		aes_same_csr_outstanding	8.000s	94.502us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	132.055us	5	5	100.00
		aes_csr_rw	13.000s	74.767us	20	20	100.00
		aes_csr_aliasing	5.000s	123.437us	5	5	100.00
		aes_same_csr_outstanding	8.000s	94.502us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	25.000s	680.171us	50	50	100.00
V2S	fault_inject	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	10.000s	389.876us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	794.687us	5	5	100.00
		aes_tl_intg_err	15.000s	369.029us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	369.029us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	1.929ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	185.829us	50	50	100.00
		aes_stress	35.000s	2.934ms	50	50	100.00
		aes_alert_reset	28.000s	1.929ms	50	50	100.00
		aes_core_fi	3.850m	10.025ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	88.490us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	94.534us	50	50	100.00
		aes_stress	35.000s	2.934ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	35.000s	2.934ms	50	50	100.00
		aes_sideload	20.000s	231.934us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	94.534us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	94.534us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	94.534us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	94.534us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	94.534us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	35.000s	2.934ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	35.000s	2.934ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	36.000s	3.109ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	36.000s	3.109ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.010ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	36.000s	3.109ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	1.929ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_ctr_fi	19.000s	80.942us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	36.000s	3.109ms	50	50	100.00
		aes_control_fi	48.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.010ms	339	350	96.86
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.317m	26.311ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.26	98.49	96.21	99.33	95.71	97.72	97.04	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test aes_control_fi has 13 failures.
  - 48.aes_control_fi.113958271939436591361438997678672096866710764121817454026625542079166447319502
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job ID: smart:bbc3bad2-e6e8-42cb-85a1-94b56dbf1eb4
```
  - 61.aes_control_fi.33736514126681694615166488576044128093406601029723378737112313292863802552310
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  Job ID: smart:f930c67d-23ce-409b-82f2-d9bc41338090
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 16.aes_cipher_fi.82189936552133512351679737547617503800686362377473616015011939101381192336024
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016447215 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016447215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 89.aes_cipher_fi.69443333890993734842788368982484913558041998434328550402325792682330531610512
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010237895 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010237895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.39024202191679337606856028409350540296215111602801959156865121138000899231694
Line 1247, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 899710678 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 899710678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.39662407390592411061971297260631098219830032711399378683897433459586366576862
Line 1073, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4146705061 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4146705061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 8.aes_core_fi.74468820213581396902547313283272640182969512107443429196831145054626021715094
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003837986 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003837986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.99177474627915754664835108876363157071810092500478295151627725571910207392294
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006482702 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006482702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 72.aes_control_fi.106536130998542105923780867903988250524556701863014570314107523466767749223269
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005795505 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005795505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 114.aes_control_fi.11480515453738775140907656959213871357487024357733784775378264469732360916852
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015721411 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015721411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

5.aes_stress_all_with_rand_reset.72798449455406482853731276698946867089217386289133434258730758027243082958942
Line 935, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 486171367 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 486171367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.60790752488830219359617790423666962665693883392541858526245939443823843882367
Line 1290, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1385502631 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1385502631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 58.aes_core_fi.64459929458322688358421721728121362378881727598646249297536289123731397271235
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024902950 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xa8978584) == 0x0
  UVM_INFO @ 10024902950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```