AES/MASKED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	69.965us	1	1	100.00
V1	smoke	aes_smoke	14.000s	154.300us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	63.151us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	56.502us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	3.647ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	285.084us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	70.410us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	56.502us	20	20	100.00
		aes_csr_aliasing	5.000s	285.084us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	154.300us	50	50	100.00
		aes_config_error	40.000s	2.151ms	50	50	100.00
		aes_stress	43.000s	1.896ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	154.300us	50	50	100.00
		aes_config_error	40.000s	2.151ms	50	50	100.00
		aes_stress	43.000s	1.896ms	50	50	100.00
V2	back2back	aes_stress	43.000s	1.896ms	50	50	100.00
		aes_b2b	50.000s	2.157ms	50	50	100.00
V2	backpressure	aes_stress	43.000s	1.896ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	154.300us	50	50	100.00
		aes_config_error	40.000s	2.151ms	50	50	100.00
		aes_stress	43.000s	1.896ms	50	50	100.00
		aes_alert_reset	4.517m	9.368ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	19.000s	836.501us	50	50	100.00
		aes_config_error	40.000s	2.151ms	50	50	100.00
		aes_alert_reset	4.517m	9.368ms	50	50	100.00
V2	trigger_clear_test	aes_clear	6.600m	9.318ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	16.000s	172.673us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.517m	9.368ms	50	50	100.00
V2	stress	aes_stress	43.000s	1.896ms	50	50	100.00
V2	sideload	aes_stress	43.000s	1.896ms	50	50	100.00
		aes_sideload	20.000s	273.465us	50	50	100.00
V2	deinitialization	aes_deinit	26.000s	1.680ms	50	50	100.00
V2	stress_all	aes_stress_all	13.783m	32.163ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	79.650us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	193.101us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	193.101us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	63.151us	5	5	100.00
		aes_csr_rw	8.000s	56.502us	20	20	100.00
		aes_csr_aliasing	5.000s	285.084us	5	5	100.00
		aes_same_csr_outstanding	4.000s	149.366us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	63.151us	5	5	100.00
		aes_csr_rw	8.000s	56.502us	20	20	100.00
		aes_csr_aliasing	5.000s	285.084us	5	5	100.00
		aes_same_csr_outstanding	4.000s	149.366us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.833m	12.331ms	49	50	98.00
V2S	fault_inject	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	329.609us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	936.386us	5	5	100.00
		aes_tl_intg_err	8.000s	184.277us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	184.277us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.517m	9.368ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	154.300us	50	50	100.00
		aes_stress	43.000s	1.896ms	50	50	100.00
		aes_alert_reset	4.517m	9.368ms	50	50	100.00
		aes_core_fi	33.000s	10.287ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	68.654us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	72.359us	50	50	100.00
		aes_stress	43.000s	1.896ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	43.000s	1.896ms	50	50	100.00
		aes_sideload	20.000s	273.465us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	72.359us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	72.359us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	72.359us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	72.359us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	72.359us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	43.000s	1.896ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	43.000s	1.896ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.000m	2.805ms	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.000m	2.805ms	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.005ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.000m	2.805ms	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.517m	9.368ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_ctr_fi	19.000s	289.474us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.000m	2.805ms	48	50	96.00
		aes_control_fi	49.000s	10.023ms	284	300	94.67
		aes_cipher_fi	49.000s	10.005ms	336	350	96.00
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.033m	8.247ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.57	96.37	99.45	95.76	97.72	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test aes_control_fi has 7 failures.
  - 55.aes_control_fi.86082312776822589750758961144380970323493148702400528034213304351477301499046
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:0daf590d-04f1-4406-a25b-7b87037f748c
```
  - 86.aes_control_fi.57931018723201257515460497679653294038472845214559277602500458966643184117066
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/86.aes_control_fi/latest/run.log
```
  Job ID: smart:dda8f91c-7855-49f4-8bde-1154614b1049
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 4 failures.
  - 103.aes_cipher_fi.56361139705677139414419958691788881310909950169743799158296921055689737816402
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/103.aes_cipher_fi/latest/run.log
```
  Job ID: smart:39c38303-df78-4e7e-9211-d66f0a92ced9
```
  - 172.aes_cipher_fi.34724350548555696044340916824694008570268446370364967729102654537044976810036
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/172.aes_cipher_fi/latest/run.log
```
  Job ID: smart:96b3b512-0f34-4986-bea8-a1dda07a986f
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 27.aes_cipher_fi.77233981126000677017145771268764205952358085704493008886763530912126268465223
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030124869 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030124869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_cipher_fi.14661437551238408329341382953996770578472851265544469487634811074700399605372
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10038373489 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038373489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 29.aes_control_fi.29250069992547543497317037723646694573015579553930080679078984818010779490842
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008602037 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008602037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 74.aes_control_fi.62700948561859559373322467443763370660788906990011402545557545662076536006388
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012085070 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012085070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.92068465588943649262736647546021238262327312411206384027661251549170645706152
Line 796, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 327580508 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 327580508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.98907038339351237167260623216738271074432826888356388656314868480331718612971
Line 1053, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 446693937 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 446693937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 1.aes_core_fi.101419793201779507753147284458901456743707526793688688763219526931564727525676
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012704395 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012704395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.7519287683169664985720166345471554072958992296507072570701072271602242737913
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013783468 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013783468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

18.aes_fi.71805272505809707856534740690212381057378811017723744119222021681732517430318
Line 4639, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_fi/latest/run.log

  UVM_FATAL @ 846807308 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 846807308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.aes_fi.112286486611039625617314333567115644695406545476791581293267760041201913691746
Line 7647, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_fi/latest/run.log

  UVM_FATAL @ 321926863 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 321926863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.53013914654527711844114266677309529766461337362288360565299560662616863276906
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1558808727 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1558808727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.104268166791491243015487023543815801314270446049280923752548397435644584254674
    Line 1040, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 509303271 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 509303271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 17.aes_reseed.78649155842596049782424718577230276699800673288635256572861463907608336295156
    Line 340, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_reseed/latest/run.log
```
  UVM_FATAL @  11881051 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  11881051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```