AES/MASKED Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	63.908us	1	1	100.00
V1	smoke	aes_smoke	29.000s	1.765ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.339us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	54.488us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.201ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	378.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	145.440us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	54.488us	20	20	100.00
		aes_csr_aliasing	5.000s	378.179us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	29.000s	1.765ms	50	50	100.00
		aes_config_error	16.000s	87.727us	50	50	100.00
		aes_stress	39.000s	2.172ms	50	50	100.00
V2	key_length	aes_smoke	29.000s	1.765ms	50	50	100.00
		aes_config_error	16.000s	87.727us	50	50	100.00
		aes_stress	39.000s	2.172ms	50	50	100.00
V2	back2back	aes_stress	39.000s	2.172ms	50	50	100.00
		aes_b2b	39.000s	477.524us	50	50	100.00
V2	backpressure	aes_stress	39.000s	2.172ms	50	50	100.00
V2	multi_message	aes_smoke	29.000s	1.765ms	50	50	100.00
		aes_config_error	16.000s	87.727us	50	50	100.00
		aes_stress	39.000s	2.172ms	50	50	100.00
		aes_alert_reset	25.000s	3.337ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	117.107us	50	50	100.00
		aes_config_error	16.000s	87.727us	50	50	100.00
		aes_alert_reset	25.000s	3.337ms	50	50	100.00
V2	trigger_clear_test	aes_clear	3.733m	7.259ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	304.919us	1	1	100.00
V2	reset_recovery	aes_alert_reset	25.000s	3.337ms	50	50	100.00
V2	stress	aes_stress	39.000s	2.172ms	50	50	100.00
V2	sideload	aes_stress	39.000s	2.172ms	50	50	100.00
		aes_sideload	11.000s	825.349us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	975.297us	50	50	100.00
V2	stress_all	aes_stress_all	2.200m	1.466ms	8	10	80.00
V2	alert_test	aes_alert_test	7.000s	84.029us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	90.237us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	90.237us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.339us	5	5	100.00
		aes_csr_rw	3.000s	54.488us	20	20	100.00
		aes_csr_aliasing	5.000s	378.179us	5	5	100.00
		aes_same_csr_outstanding	4.000s	166.023us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.339us	5	5	100.00
		aes_csr_rw	3.000s	54.488us	20	20	100.00
		aes_csr_aliasing	5.000s	378.179us	5	5	100.00
		aes_same_csr_outstanding	4.000s	166.023us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	42.000s	1.409ms	49	50	98.00
V2S	fault_inject	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	267.732us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	598.836us	5	5	100.00
		aes_tl_intg_err	6.000s	1.603ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.603ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	25.000s	3.337ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	29.000s	1.765ms	50	50	100.00
		aes_stress	39.000s	2.172ms	50	50	100.00
		aes_alert_reset	25.000s	3.337ms	50	50	100.00
		aes_core_fi	14.000s	82.482us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	62.759us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	98.098us	50	50	100.00
		aes_stress	39.000s	2.172ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	39.000s	2.172ms	50	50	100.00
		aes_sideload	11.000s	825.349us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	98.098us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	98.098us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	98.098us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	98.098us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	98.098us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	39.000s	2.172ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	39.000s	2.172ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	34.000s	1.345ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	34.000s	1.345ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	34.000s	1.345ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	25.000s	3.337ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_ctr_fi	9.000s	64.738us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	34.000s	1.345ms	50	50	100.00
		aes_control_fi	27.000s	10.023ms	281	300	93.67
		aes_cipher_fi	48.000s	10.005ms	333	350	95.14
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	8.183m	13.374ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.28	99.45	95.80	97.64	100.00	98.96	95.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 16 failures.
  - 47.aes_control_fi.47817852622774351801656443803529160614436138861552817663641453081328240547693
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  Job ID: smart:6a089010-4815-4f5b-922b-34b806b3a1b9
```
  - 75.aes_control_fi.96718218354499282128872675718038241722144232801938601055400783189776941397641
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  Job ID: smart:da87a7ec-705e-42e2-933b-4f142fd486c1
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 5 failures.
  - 160.aes_cipher_fi.16492325039180753877200265279234657297357246409501547160402908660574286071873
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/160.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ca5fae44-bd48-46e7-9c9e-599edf743ccc
```
  - 184.aes_cipher_fi.44348213076953715836441074510415059679624633314964910118399105920918475138656
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/184.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1004d7d9-9cfe-4588-871e-06a105a5aa1d
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 69.aes_cipher_fi.3478101637569123504458472721292063878445900144569620198387208077092886999751
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022602558 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022602558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 70.aes_cipher_fi.103573760808361657946928798587304883256974279778022447991991513461346722052135
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/70.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006128619 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006128619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.110623966806201446047082836724711543766028320422313786306749825090608848204819
Line 414, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1301799680 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1301799680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.9155593867069236261504256117316134351695715245603656654119594378225378196697
Line 580, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 410820513 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 410820513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 87.aes_control_fi.105649154285739917474008230231463769514891305288550116503072638316206997271625
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/87.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023013737 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023013737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 168.aes_control_fi.110971743831751885387258880701404134395528824415008590917583820480662023632686
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/168.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022019855 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022019855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.96786933656965562289433710706390441354164033047388240469585982398231647299300
Line 1416, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4368491533 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4368491533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.88876995320606318195901455696060103809834919499565123793133253549719586870757
Line 1400, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2975301281 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2975301281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.47084562246365546759005815055000777805444542600507011246774204793667495072204
    Line 47373, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 1745728877 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1745728877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_reseed has 1 failures.
  - 32.aes_reseed.76067051544575795236470976538947787262197171019604257540282393313748889305831
    Line 1795, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_reseed/latest/run.log
```
  UVM_FATAL @ 136439029 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 136439029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

5.aes_stress_all.38122184575223354738120679444778769703121058985758721764005276108922773014554
Line 172281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 965908332 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 965888332 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 965908332 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 965888332 PS)
  UVM_ERROR @ 965908332 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut