AES/MASKED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	13.000s	659.606us	1	1	100.00
V1	smoke	aes_smoke	9.000s	65.719us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	118.778us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	67.883us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.892ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	156.671us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	210.856us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	67.883us	20	20	100.00
		aes_csr_aliasing	4.000s	156.671us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	65.719us	50	50	100.00
		aes_config_error	3.950m	6.889ms	50	50	100.00
		aes_stress	44.000s	1.211ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	65.719us	50	50	100.00
		aes_config_error	3.950m	6.889ms	50	50	100.00
		aes_stress	44.000s	1.211ms	50	50	100.00
V2	back2back	aes_stress	44.000s	1.211ms	50	50	100.00
		aes_b2b	36.000s	404.099us	50	50	100.00
V2	backpressure	aes_stress	44.000s	1.211ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	65.719us	50	50	100.00
		aes_config_error	3.950m	6.889ms	50	50	100.00
		aes_stress	44.000s	1.211ms	50	50	100.00
		aes_alert_reset	1.967m	4.063ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	294.301us	50	50	100.00
		aes_config_error	3.950m	6.889ms	50	50	100.00
		aes_alert_reset	1.967m	4.063ms	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	434.452us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	337.417us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.967m	4.063ms	50	50	100.00
V2	stress	aes_stress	44.000s	1.211ms	50	50	100.00
V2	sideload	aes_stress	44.000s	1.211ms	50	50	100.00
		aes_sideload	13.000s	730.736us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	311.827us	50	50	100.00
V2	stress_all	aes_stress_all	17.383m	34.382ms	10	10	100.00
V2	alert_test	aes_alert_test	12.000s	98.385us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	103.924us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	103.924us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	118.778us	5	5	100.00
		aes_csr_rw	8.000s	67.883us	20	20	100.00
		aes_csr_aliasing	4.000s	156.671us	5	5	100.00
		aes_same_csr_outstanding	9.000s	218.007us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	118.778us	5	5	100.00
		aes_csr_rw	8.000s	67.883us	20	20	100.00
		aes_csr_aliasing	4.000s	156.671us	5	5	100.00
		aes_same_csr_outstanding	9.000s	218.007us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	18.000s	516.282us	49	50	98.00
V2S	fault_inject	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	95.653us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	18.000s	3.056ms	5	5	100.00
		aes_tl_intg_err	9.000s	128.143us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	128.143us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.967m	4.063ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	65.719us	50	50	100.00
		aes_stress	44.000s	1.211ms	50	50	100.00
		aes_alert_reset	1.967m	4.063ms	50	50	100.00
		aes_core_fi	11.000s	424.763us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	103.213us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	63.369us	50	50	100.00
		aes_stress	44.000s	1.211ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	44.000s	1.211ms	50	50	100.00
		aes_sideload	13.000s	730.736us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	63.369us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	63.369us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	63.369us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	63.369us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	63.369us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	44.000s	1.211ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	44.000s	1.211ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	118.112us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	118.112us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.005ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	118.112us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.967m	4.063ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_ctr_fi	8.000s	92.004us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	118.112us	49	50	98.00
		aes_control_fi	51.000s	10.005ms	276	300	92.00
		aes_cipher_fi	52.000s	10.005ms	341	350	97.43
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	8.533m	26.584ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.53	96.25	99.42	95.71	97.72	97.78	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 18 failures.
  - 20.aes_control_fi.99270602346639150441677804445345695297619503975830408474353507015104916129665
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:9abf03fd-ce64-4f33-8493-64b862db1674
```
  - 25.aes_control_fi.62127086083059124929990489485533301802547125992791176138500249686125176535761
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:14e802f7-823a-4c92-ad05-7e231ae6c179
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 4 failures.
  - 146.aes_cipher_fi.97548310590770719747774670078452402588863685356965438114954567867822782332930
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/146.aes_cipher_fi/latest/run.log
```
  Job ID: smart:27f1d182-b4d5-4318-a902-dd70a8b78df9
```
  - 155.aes_cipher_fi.16786211895241803089645859472118824049349011023650521513185617697129163476433
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/155.aes_cipher_fi/latest/run.log
```
  Job ID: smart:73e49acf-5788-4184-b123-56781deca722
```
  - ... and 2 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 52.aes_control_fi.69038702942584279348870559147044980345550549287363357721658487567642616370733
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004917012 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004917012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.aes_control_fi.39729277104477584717149272395728912023034348533181400949717507651365734811996
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007349242 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007349242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 7.aes_cipher_fi.57737265564312660691351965514962308076185503081126013170811466185141926823343
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017975192 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017975192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 113.aes_cipher_fi.57358642408093986165514569443598830123247745786666623788155625668644746736987
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004936019 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004936019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.21711520364152661537797148056551414002845240430393205204229247349281487824179
Line 1832, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5553613952 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5553613952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.5054991917923440715430460093367035562247278961525611867048096537367228566602
Line 1170, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1565606270 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1565606270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.87676099387304661699475110941314981863542325821703376242412697329716511115299
Line 860, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 352550466 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 352550466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.96115711353132437890240516994279175622251105951874529543972816474929340947240
Line 1645, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26584280542 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 26584280542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 0.aes_fi.27065517476374769249848189818525072683762386077229749391997278609882193651860
    Line 4138, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 23824116 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 23803283 PS)
  UVM_ERROR @  23824116 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  23824116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.11563758900739119103047432073719451721985937669669132500898237871763960395217
    Line 899, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1559720577 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1559720577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.89455158186782900694494528080473901970471215235661230032945308043861792680642
    Line 1006, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1141654859 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1141654859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.69486188798517937474303355846847312255935514231803032550721451044467928030943
    Line 504, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6620425476 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6620425476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 44.aes_reseed.51498945283969836390594742632449625529197423245492115185040922736202268802648
    Line 377, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_reseed/latest/run.log
```
  UVM_FATAL @  71382207 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  71382207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```