AES/MASKED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	70.174us	1	1	100.00
V1	smoke	aes_smoke	27.000s	965.183us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	103.600us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	104.058us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	6.705ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	279.604us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	126.210us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	104.058us	20	20	100.00
		aes_csr_aliasing	5.000s	279.604us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	27.000s	965.183us	50	50	100.00
		aes_config_error	12.000s	336.050us	50	50	100.00
		aes_stress	28.000s	749.018us	50	50	100.00
V2	key_length	aes_smoke	27.000s	965.183us	50	50	100.00
		aes_config_error	12.000s	336.050us	50	50	100.00
		aes_stress	28.000s	749.018us	50	50	100.00
V2	back2back	aes_stress	28.000s	749.018us	50	50	100.00
		aes_b2b	41.000s	514.497us	50	50	100.00
V2	backpressure	aes_stress	28.000s	749.018us	50	50	100.00
V2	multi_message	aes_smoke	27.000s	965.183us	50	50	100.00
		aes_config_error	12.000s	336.050us	50	50	100.00
		aes_stress	28.000s	749.018us	50	50	100.00
		aes_alert_reset	21.000s	1.539ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	242.970us	50	50	100.00
		aes_config_error	12.000s	336.050us	50	50	100.00
		aes_alert_reset	21.000s	1.539ms	50	50	100.00
V2	trigger_clear_test	aes_clear	57.000s	6.129ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	30.000s	2.621ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	1.539ms	50	50	100.00
V2	stress	aes_stress	28.000s	749.018us	50	50	100.00
V2	sideload	aes_stress	28.000s	749.018us	50	50	100.00
		aes_sideload	19.000s	1.613ms	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	1.182ms	50	50	100.00
V2	stress_all	aes_stress_all	1.633m	1.282ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	59.895us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	432.427us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	432.427us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	103.600us	5	5	100.00
		aes_csr_rw	4.000s	104.058us	20	20	100.00
		aes_csr_aliasing	5.000s	279.604us	5	5	100.00
		aes_same_csr_outstanding	13.000s	125.140us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	103.600us	5	5	100.00
		aes_csr_rw	4.000s	104.058us	20	20	100.00
		aes_csr_aliasing	5.000s	279.604us	5	5	100.00
		aes_same_csr_outstanding	13.000s	125.140us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	17.000s	785.735us	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	159.675us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	1.346ms	5	5	100.00
		aes_tl_intg_err	6.000s	295.869us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	295.869us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	1.539ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	27.000s	965.183us	50	50	100.00
		aes_stress	28.000s	749.018us	50	50	100.00
		aes_alert_reset	21.000s	1.539ms	50	50	100.00
		aes_core_fi	1.567m	10.003ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	263.217us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	468.512us	50	50	100.00
		aes_stress	28.000s	749.018us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	28.000s	749.018us	50	50	100.00
		aes_sideload	19.000s	1.613ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	468.512us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	468.512us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	468.512us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	468.512us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	468.512us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	28.000s	749.018us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	28.000s	749.018us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	3.866ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	3.866ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.009ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	3.866ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	1.539ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_ctr_fi	4.000s	289.518us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	3.866ms	50	50	100.00
		aes_control_fi	46.000s	10.005ms	271	300	90.33
		aes_cipher_fi	49.000s	10.009ms	330	350	94.29
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.383m	64.977ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.54	96.30	99.45	95.72	97.72	100.00	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_control_fi has 17 failures.
  - 0.aes_control_fi.77899193783839145246108909262454521157095647514763219687027974883910267556615
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:93c5bb97-8c8e-494b-a456-3d7ec30fe4be
```
  - 20.aes_control_fi.57507867301913917523111754377756835415691774170215549119891438433385271529447
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:c4afc71e-3ad6-4bbb-8ac0-5d130d62638c
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 9 failures.
  - 38.aes_cipher_fi.102085298704060022727125809484511408524950087603344376421915178844316431148065
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5c1e9db1-50ab-450f-a079-2c1ac17c2850
```
  - 161.aes_cipher_fi.37316220003932813658383399812827942499217991868524054613287556334117573146850
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/161.aes_cipher_fi/latest/run.log
```
  Job ID: smart:51bb09b0-9d15-4f7d-ab3c-00c0dce10bc7
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 16.aes_control_fi.109759613103556248401327943546958593787704340601353399989935062265202929905892
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10142830761 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10142830761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_control_fi.28734328362246343560614894323348934670290130841760505249073459964903139820005
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009809240 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009809240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 3.aes_cipher_fi.96752639004372227146322095039980972435562378810887308176061113076983124699618
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008796447 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008796447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.aes_cipher_fi.47281454522625170406842594975617238535158616159271497282536524910257025442742
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10076318895 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10076318895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.22277020869952623123094945398810940535105014184236467473045622417237734983940
Line 1624, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3424756613 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3424756613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.57418389386794562139632619599148986812800562272014500690961135007072886191510
Line 696, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 64976835021 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 64976835021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.56366873066705325244498081823778534048909200973678006397358693179850303199872
Line 1718, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1926507221 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1926507221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.17257601169348512909322963760680089010388222196566606819205134353438911489611
Line 835, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2471746947 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2471746947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 18.aes_core_fi.71568832465151271426052679697095008995626568456236980682863454439891735534843
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002515389 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002515389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.77605801085508788654892600550254807412936881744630042417330822661458654530898
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003211477 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003211477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 326.aes_cipher_fi.71355710106835310786239630717731693800509747885882068593938208345521798626747
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/326.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  10007299 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  10007299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```