AES/MASKED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	73.928us	1	1	100.00
V1	smoke	aes_smoke	11.000s	256.568us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	161.574us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.683m	10.016ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	2.577ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	363.119us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	9.000s	67.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.683m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	363.119us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	11.000s	256.568us	50	50	100.00
		aes_config_error	1.217m	4.593ms	50	50	100.00
		aes_stress	50.000s	13.181ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	256.568us	50	50	100.00
		aes_config_error	1.217m	4.593ms	50	50	100.00
		aes_stress	50.000s	13.181ms	50	50	100.00
V2	back2back	aes_stress	50.000s	13.181ms	50	50	100.00
		aes_b2b	58.000s	663.572us	50	50	100.00
V2	backpressure	aes_stress	50.000s	13.181ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	256.568us	50	50	100.00
		aes_config_error	1.217m	4.593ms	50	50	100.00
		aes_stress	50.000s	13.181ms	50	50	100.00
		aes_alert_reset	1.450m	3.244ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	57.199us	50	50	100.00
		aes_config_error	1.217m	4.593ms	50	50	100.00
		aes_alert_reset	1.450m	3.244ms	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	1.338ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	16.000s	577.639us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.450m	3.244ms	50	50	100.00
V2	stress	aes_stress	50.000s	13.181ms	50	50	100.00
V2	sideload	aes_stress	50.000s	13.181ms	50	50	100.00
		aes_sideload	29.000s	1.166ms	50	50	100.00
V2	deinitialization	aes_deinit	30.000s	958.302us	50	50	100.00
V2	stress_all	aes_stress_all	5.467m	40.932ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	214.213us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	13.000s	81.314us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	13.000s	81.314us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	161.574us	5	5	100.00
		aes_csr_rw	1.683m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	363.119us	5	5	100.00
		aes_same_csr_outstanding	9.000s	1.315ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	161.574us	5	5	100.00
		aes_csr_rw	1.683m	10.016ms	19	20	95.00
		aes_csr_aliasing	5.000s	363.119us	5	5	100.00
		aes_same_csr_outstanding	9.000s	1.315ms	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.167m	6.445ms	48	50	96.00
V2S	fault_inject	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	344.817us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	2.305ms	5	5	100.00
		aes_tl_intg_err	10.000s	648.798us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	648.798us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.450m	3.244ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	256.568us	50	50	100.00
		aes_stress	50.000s	13.181ms	50	50	100.00
		aes_alert_reset	1.450m	3.244ms	50	50	100.00
		aes_core_fi	1.217m	10.014ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	91.860us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	65.515us	50	50	100.00
		aes_stress	50.000s	13.181ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	50.000s	13.181ms	50	50	100.00
		aes_sideload	29.000s	1.166ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	65.515us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	65.515us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	65.515us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	65.515us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	65.515us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	50.000s	13.181ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	50.000s	13.181ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	2.471ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	2.471ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	2.471ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.450m	3.244ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_ctr_fi	4.000s	60.181us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	2.471ms	49	50	98.00
		aes_control_fi	43.000s	10.010ms	280	300	93.33
		aes_cipher_fi	49.000s	10.006ms	338	350	96.57
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.033m	18.849ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.45	95.74	97.72	100.00	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 13 failures.
  - 13.aes_control_fi.31836402539761812927385460227028557650332742284122896939412914706879205426999
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:75f0d2f0-7312-4424-9b1a-2b7da61f2c4a
```
  - 22.aes_control_fi.35468098696348207488090912351122466545085870296519991907096384012367434323049
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:5b8e1b59-6fe9-4f0c-a71b-e045cbef2155
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 3 failures.
  - 114.aes_cipher_fi.31328856019782588987088779385725172647910012316033461713435022189765125256922
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5ca88dce-020c-459f-9989-e9a7ce63ef4d
```
  - 260.aes_cipher_fi.63851382261407915899195424665316292087736576832199927859639588199430759956565
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/260.aes_cipher_fi/latest/run.log
```
  Job ID: smart:926804b8-ae0e-4c0b-885a-1d572f9cbf78
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.49680510778415895929266652047523704398773231887812380657853362789762171366601
Line 650, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1885448856 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1885448856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.20620967560243613332594184059785896205304994170744866584324244975803191036531
Line 1363, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4826758221 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4826758221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 1.aes_cipher_fi.39055337844503981028588997915705335866817590822354918799664721163152488738129
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015742985 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015742985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 98.aes_cipher_fi.105388035210604373880541421249276547231388688025821376795757955687311372314680
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/98.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10035426379 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035426379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 26.aes_control_fi.56860787615115534322290097686644144419139139614763760930887409951649037118276
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010437883 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010437883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_control_fi.37835116121498832658101392136123632754311384458060088490103056665596288393370
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10052869857 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10052869857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 18.aes_core_fi.104471776879151823871597528822799546259809288640740853210971646798370008280186
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013761555 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013761555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_core_fi.95871212043689803602033952971316870456277023856870721258371022884520561666292
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007419291 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007419291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 3.aes_reseed.98435598766477662791354616513284684075510626391980965579569139768209613927486
    Line 1334, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_reseed/latest/run.log
```
  UVM_FATAL @  62860220 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  62860220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.57447358494434289117403240180956648386468385741229907394882646149892377654640
    Line 573, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 401109378 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 401109378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 8.aes_csr_rw.90630382151075717105909769667468622482836708289103734318223265635887074673785
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10015775341 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1b612284) == 0x0
  UVM_INFO @ 10015775341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 25.aes_fi.20235042680278170047252096440858212656644382809004583254850509771298129572317
    Line 4187, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 191075949 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 190875949 PS)
  UVM_ERROR @ 191075949 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 191075949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 35.aes_reseed.45368710942204620120640570432054425650672313065509799951123073228900093360455
    Line 1944, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_reseed/latest/run.log
```
  UVM_FATAL @  50244903 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  50244903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```