AES/MASKED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	57.764us	1	1	100.00
V1	smoke	aes_smoke	13.000s	103.463us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	92.512us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	94.503us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	796.759us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	176.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	9.000s	76.534us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	94.503us	20	20	100.00
		aes_csr_aliasing	4.000s	176.152us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	103.463us	50	50	100.00
		aes_config_error	1.033m	2.056ms	50	50	100.00
		aes_stress	39.000s	2.181ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	103.463us	50	50	100.00
		aes_config_error	1.033m	2.056ms	50	50	100.00
		aes_stress	39.000s	2.181ms	50	50	100.00
V2	back2back	aes_stress	39.000s	2.181ms	50	50	100.00
		aes_b2b	34.000s	290.506us	50	50	100.00
V2	backpressure	aes_stress	39.000s	2.181ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	103.463us	50	50	100.00
		aes_config_error	1.033m	2.056ms	50	50	100.00
		aes_stress	39.000s	2.181ms	50	50	100.00
		aes_alert_reset	11.000s	106.018us	49	50	98.00
V2	failure_test	aes_man_cfg_err	14.000s	83.353us	50	50	100.00
		aes_config_error	1.033m	2.056ms	50	50	100.00
		aes_alert_reset	11.000s	106.018us	49	50	98.00
V2	trigger_clear_test	aes_clear	33.000s	952.849us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	2.848ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	106.018us	49	50	98.00
V2	stress	aes_stress	39.000s	2.181ms	50	50	100.00
V2	sideload	aes_stress	39.000s	2.181ms	50	50	100.00
		aes_sideload	28.000s	1.680ms	50	50	100.00
V2	deinitialization	aes_deinit	19.000s	165.037us	50	50	100.00
V2	stress_all	aes_stress_all	1.983m	40.621ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	60.783us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	93.256us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	93.256us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	92.512us	5	5	100.00
		aes_csr_rw	7.000s	94.503us	20	20	100.00
		aes_csr_aliasing	4.000s	176.152us	5	5	100.00
		aes_same_csr_outstanding	8.000s	55.690us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	92.512us	5	5	100.00
		aes_csr_rw	7.000s	94.503us	20	20	100.00
		aes_csr_aliasing	4.000s	176.152us	5	5	100.00
		aes_same_csr_outstanding	8.000s	55.690us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	1.349ms	49	50	98.00
V2S	fault_inject	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	99.496us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	19.000s	3.960ms	5	5	100.00
		aes_tl_intg_err	12.000s	674.878us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	12.000s	674.878us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	106.018us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	103.463us	50	50	100.00
		aes_stress	39.000s	2.181ms	50	50	100.00
		aes_alert_reset	11.000s	106.018us	49	50	98.00
		aes_core_fi	1.550m	10.004ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	133.870us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	82.996us	50	50	100.00
		aes_stress	39.000s	2.181ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	39.000s	2.181ms	50	50	100.00
		aes_sideload	28.000s	1.680ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	82.996us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	82.996us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	82.996us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	82.996us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	82.996us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	39.000s	2.181ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	39.000s	2.181ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	309.169us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	309.169us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.009ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	309.169us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	106.018us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_ctr_fi	9.000s	99.586us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	309.169us	50	50	100.00
		aes_control_fi	46.000s	10.005ms	281	300	93.67
		aes_cipher_fi	52.000s	10.009ms	329	350	94.00
V2S		TOTAL			941	985	95.53
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.250m	1.951ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1547	1602	96.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.57	96.37	99.45	95.91	97.64	100.00	98.96	95.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 14 failures.
  - 29.aes_control_fi.17434529662260935792316185335042570755166083511526085265713815599472909291193
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:8abd285c-a34e-4134-9c46-4c58b22fd5bb
```
  - 34.aes_control_fi.81093621560333441285595727691254626387788880565166097922039659959869298769468
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:3e5dd103-4281-4166-a7e0-b73d6478c39f
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 10 failures.
  - 32.aes_cipher_fi.61459222640664045706928717750770000297151786231542669506342537848171128003219
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4c500399-3d15-46f1-9d9d-907be99b4586
```
  - 41.aes_cipher_fi.16992626684117389139201457736509689335251928892953700190195064446593421382406
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0702fecd-3e38-41ba-8e56-da5adb8c1194
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 93.aes_cipher_fi.76955994366198059296337972310502959274872635518674254504761950287192896592250
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10042865083 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042865083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 116.aes_cipher_fi.23103154462339021110149655150784144526634029040265554453355372361015523297192
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/116.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007394483 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007394483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.54287139603247207036025538595149652592667800042039026453233037058464912004672
Line 1510, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1292541878 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1292541878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.77156731772476648200009544836379106366884307457572306571580152229070867957376
Line 1195, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2907084059 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2907084059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 55.aes_control_fi.112967213350665607043188046558851137855548032898961664607583562018855014346054
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019114165 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019114165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_control_fi.86606061247096457310445081809104036734176189994469585565133135489564255246682
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10033789309 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033789309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 24.aes_core_fi.99659728310864697054231067806950434169179960770221947042724898536206518171370
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004997990 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004997990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_core_fi.24042230729896589433208679361937006441619953162777730436067507252239724990984
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003835142 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003835142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 1.aes_reseed.44358558818443736259273160254721352313582825514121305235305685210814796322599
    Line 2411, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_reseed/latest/run.log
```
  UVM_FATAL @ 116303945 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 116303945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.47340719770826441143406248947874984492755177317256617283313437625983451375095
    Line 990, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 404072656 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 404072656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.6928188034181492539586996276882225561934624840885913102458018660732017615137
    Line 573, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 711416577 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 711416577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 35.aes_alert_reset.15056173253083283174735916862685498474218870296493347141014944304057334181987
    Line 1970, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 10128614 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10107781 PS)
  UVM_ERROR @  10128614 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  10128614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```