AES/MASKED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	70.041us	1	1	100.00
V1	smoke	aes_smoke	14.000s	1.095ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	70.768us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	52.238us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	2.310ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.067m	10.076ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	392.605us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	52.238us	20	20	100.00
		aes_csr_aliasing	3.067m	10.076ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	1.095ms	50	50	100.00
		aes_config_error	25.000s	1.587ms	50	50	100.00
		aes_stress	1.533m	4.910ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	1.095ms	50	50	100.00
		aes_config_error	25.000s	1.587ms	50	50	100.00
		aes_stress	1.533m	4.910ms	50	50	100.00
V2	back2back	aes_stress	1.533m	4.910ms	50	50	100.00
		aes_b2b	35.000s	1.250ms	50	50	100.00
V2	backpressure	aes_stress	1.533m	4.910ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	1.095ms	50	50	100.00
		aes_config_error	25.000s	1.587ms	50	50	100.00
		aes_stress	1.533m	4.910ms	50	50	100.00
		aes_alert_reset	41.000s	2.120ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	69.734us	50	50	100.00
		aes_config_error	25.000s	1.587ms	50	50	100.00
		aes_alert_reset	41.000s	2.120ms	50	50	100.00
V2	trigger_clear_test	aes_clear	21.000s	568.860us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	193.464us	1	1	100.00
V2	reset_recovery	aes_alert_reset	41.000s	2.120ms	50	50	100.00
V2	stress	aes_stress	1.533m	4.910ms	50	50	100.00
V2	sideload	aes_stress	1.533m	4.910ms	50	50	100.00
		aes_sideload	19.000s	1.051ms	50	50	100.00
V2	deinitialization	aes_deinit	23.000s	886.729us	50	50	100.00
V2	stress_all	aes_stress_all	14.100m	28.122ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	61.662us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	307.951us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	307.951us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	70.768us	5	5	100.00
		aes_csr_rw	8.000s	52.238us	20	20	100.00
		aes_csr_aliasing	3.067m	10.076ms	4	5	80.00
		aes_same_csr_outstanding	7.000s	82.001us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	70.768us	5	5	100.00
		aes_csr_rw	8.000s	52.238us	20	20	100.00
		aes_csr_aliasing	3.067m	10.076ms	4	5	80.00
		aes_same_csr_outstanding	7.000s	82.001us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	33.000s	1.292ms	50	50	100.00
V2S	fault_inject	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	97.606us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.507ms	5	5	100.00
		aes_tl_intg_err	14.000s	181.677us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	181.677us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	41.000s	2.120ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	1.095ms	50	50	100.00
		aes_stress	1.533m	4.910ms	50	50	100.00
		aes_alert_reset	41.000s	2.120ms	50	50	100.00
		aes_core_fi	1.450m	10.025ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	74.474us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	303.955us	50	50	100.00
		aes_stress	1.533m	4.910ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.533m	4.910ms	50	50	100.00
		aes_sideload	19.000s	1.051ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	303.955us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	303.955us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	303.955us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	303.955us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	303.955us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.533m	4.910ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.533m	4.910ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	35.000s	1.229ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	35.000s	1.229ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.006ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	35.000s	1.229ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	41.000s	2.120ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_ctr_fi	7.000s	192.829us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	35.000s	1.229ms	50	50	100.00
		aes_control_fi	50.000s	10.040ms	284	300	94.67
		aes_cipher_fi	47.000s	10.006ms	335	350	95.71
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.467m	8.067ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.55	96.32	99.45	95.76	97.72	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 10 failures.
  - 10.aes_control_fi.92474449967989943623334484631536577403601032092924051121835381811517847900086
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:fcf414b2-1494-4572-9cfd-1763ccc846f2
```
  - 96.aes_control_fi.47456178396858656886934408753893275112454601837815039444599315308753179702160
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  Job ID: smart:c96f98c7-3366-443e-8252-578b46617ac8
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 8 failures.
  - 93.aes_cipher_fi.10688052895038846408232204721300975992675906176327133231647465771428886015784
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6532dc1b-6e28-4d7d-9ac0-fe2aaeea90ff
```
  - 146.aes_cipher_fi.5937082132459974112108285370775750473845484410896406812348559810738482924272
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/146.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c5e1aff0-2940-43d4-92be-f56a30aa3646
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 6.aes_cipher_fi.48948650210501545625738094997563543276190855448542244798805178259564715630418
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026859262 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026859262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.aes_cipher_fi.104327008336145176730589179537416841473115876745174599379088710804674001007349
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019075544 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019075544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 5.aes_control_fi.12791061223824162675999708414661574742040662299640472641681208929948012301155
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020016178 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020016178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_control_fi.36529971392366890994242158561163113808167400524132332560799570539375375885821
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010554796 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010554796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.17698917780786369144803338732382035672521705582878132940654052509474442408494
Line 730, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2046307157 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2046307157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.30299227948457333550754749836123061163039589809459426347350829762843273891969
Line 1606, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 873658800 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 873658800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.100875682202040083133181199038257168215691130440170570211678761547705522526526
Line 1302, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 692746775 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 692746775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.18577953938801740105130514207419364300639282352142774174327992777970228462652
Line 1025, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 596288933 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 596288933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 3.aes_csr_aliasing.84105785674347362896286000055267534643521993528206053114351133552424673505349
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10076153718 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x7de41e84) == 0x0
  UVM_INFO @ 10076153718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.25762937787202424600988725938614019481944095544307927738163117251038963139779
    Line 334, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 320847398 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 320847398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 40.aes_core_fi.26320949288048625178057958322024231372883374765509018001325419593746820073750
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025001588 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025001588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```