AES/MASKED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	106.198us	1	1	100.00
V1	smoke	aes_smoke	7.000s	177.203us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	163.944us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	57.064us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	519.931us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.490ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	266.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	57.064us	20	20	100.00
		aes_csr_aliasing	5.000s	1.490ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	177.203us	50	50	100.00
		aes_config_error	22.000s	695.123us	50	50	100.00
		aes_stress	13.000s	411.942us	50	50	100.00
V2	key_length	aes_smoke	7.000s	177.203us	50	50	100.00
		aes_config_error	22.000s	695.123us	50	50	100.00
		aes_stress	13.000s	411.942us	50	50	100.00
V2	back2back	aes_stress	13.000s	411.942us	50	50	100.00
		aes_b2b	35.000s	427.914us	50	50	100.00
V2	backpressure	aes_stress	13.000s	411.942us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	177.203us	50	50	100.00
		aes_config_error	22.000s	695.123us	50	50	100.00
		aes_stress	13.000s	411.942us	50	50	100.00
		aes_alert_reset	44.000s	2.666ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	30.000s	1.174ms	50	50	100.00
		aes_config_error	22.000s	695.123us	50	50	100.00
		aes_alert_reset	44.000s	2.666ms	50	50	100.00
V2	trigger_clear_test	aes_clear	38.000s	1.032ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	2.132ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	44.000s	2.666ms	50	50	100.00
V2	stress	aes_stress	13.000s	411.942us	50	50	100.00
V2	sideload	aes_stress	13.000s	411.942us	50	50	100.00
		aes_sideload	20.000s	595.379us	50	50	100.00
V2	deinitialization	aes_deinit	4.817m	7.921ms	50	50	100.00
V2	stress_all	aes_stress_all	1.700m	12.096ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	149.704us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	142.031us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	142.031us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	163.944us	5	5	100.00
		aes_csr_rw	7.000s	57.064us	20	20	100.00
		aes_csr_aliasing	5.000s	1.490ms	5	5	100.00
		aes_same_csr_outstanding	6.383m	10.012ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	163.944us	5	5	100.00
		aes_csr_rw	7.000s	57.064us	20	20	100.00
		aes_csr_aliasing	5.000s	1.490ms	5	5	100.00
		aes_same_csr_outstanding	6.383m	10.012ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.900m	15.567ms	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	248.416us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	882.817us	5	5	100.00
		aes_tl_intg_err	10.000s	490.625us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	490.625us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	44.000s	2.666ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	177.203us	50	50	100.00
		aes_stress	13.000s	411.942us	50	50	100.00
		aes_alert_reset	44.000s	2.666ms	50	50	100.00
		aes_core_fi	18.000s	10.021ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	72.450us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	228.415us	50	50	100.00
		aes_stress	13.000s	411.942us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	411.942us	50	50	100.00
		aes_sideload	20.000s	595.379us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	228.415us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	228.415us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	228.415us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	228.415us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	228.415us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	411.942us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	411.942us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	583.482us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	583.482us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.102ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	583.482us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	44.000s	2.666ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_ctr_fi	13.000s	61.204us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	583.482us	50	50	100.00
		aes_control_fi	45.000s	10.005ms	282	300	94.00
		aes_cipher_fi	42.000s	10.102ms	336	350	96.00
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.533m	4.018ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	98.49	96.21	99.35	95.83	97.72	98.52	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_cipher_fi has 10 failures.
  - 21.aes_cipher_fi.67959827524250662499011151553373278832465385656391038141887258177990057144804
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d469ea12-3a87-4f7e-a86b-43ccfffc0a3a
```
  - 53.aes_cipher_fi.7607861634608991124704412731835752970603462624867529640135252423716574134117
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_cipher_fi/latest/run.log
```
  Job ID: smart:69c94df5-a9b8-497e-acb8-5b0f7c4f6f6f
```
  - ... and 8 more failures.
- Test aes_control_fi has 13 failures.
  - 58.aes_control_fi.17087231097638731637955841053383916015874452986259978382697412477443178561840
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job ID: smart:4e49ddd2-806d-462d-876f-cfba9cacdcff
```
  - 98.aes_control_fi.97941991501380440110718023083095224914675196457196406073453344486020609745898
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/98.aes_control_fi/latest/run.log
```
  Job ID: smart:98582bb8-2509-4067-b1ea-5d58d85d230e
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.67336585477786058400686951177200398601699978401223973170436336091188274204612
Line 724, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1389331206 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1389331206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.84229932925002770127660295877227299032125281495397399517246137984103991157993
Line 2229, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4018415635 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4018415635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 45.aes_control_fi.90334889533808766390635052875250493637480449415052400358210158135715937917594
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013452450 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013452450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 91.aes_control_fi.107876873345901949919701063675750869053494667140379158679935871589807999482897
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/91.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005108056 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005108056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 57.aes_cipher_fi.65856469863166920571195282360413039215129675002873955351181666426523595109789
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022036814 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022036814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 114.aes_cipher_fi.85000868658781702448237839330162384174810574945675641212232229218543954459221
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014358096 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014358096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.15372565271764449514609650327683961255419161650021328316960199043223070914324
Line 1791, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4383783236 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4383783236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.73028844323804119592958721016353395606018397550675001711281480206281628970137
Line 1103, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3683343919 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3683343919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.10733389371785922968246548425775449205951851746313543032606572599627589255742
    Line 535, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1617865775 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1617865775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 14.aes_same_csr_outstanding.61007130601926283597531394319771429049892828162210766277387342046094715635376
    Line 297, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10012065667 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xf3d2f084) == 0x0
  UVM_INFO @ 10012065667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 15.aes_core_fi.35941256965022882350817359211140427918672958916916421481662581749295035666760
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021421481 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021421481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```