AES/MASKED Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	123.072us	1	1	100.00
V1	smoke	aes_smoke	11.000s	1.025ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	93.471us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	53.291us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.594ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	89.584us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	105.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	53.291us	20	20	100.00
		aes_csr_aliasing	5.000s	89.584us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	1.025ms	50	50	100.00
		aes_config_error	20.000s	2.337ms	50	50	100.00
		aes_stress	30.000s	1.677ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	1.025ms	50	50	100.00
		aes_config_error	20.000s	2.337ms	50	50	100.00
		aes_stress	30.000s	1.677ms	50	50	100.00
V2	back2back	aes_stress	30.000s	1.677ms	50	50	100.00
		aes_b2b	39.000s	484.059us	50	50	100.00
V2	backpressure	aes_stress	30.000s	1.677ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	1.025ms	50	50	100.00
		aes_config_error	20.000s	2.337ms	50	50	100.00
		aes_stress	30.000s	1.677ms	50	50	100.00
		aes_alert_reset	12.000s	447.197us	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	410.867us	50	50	100.00
		aes_config_error	20.000s	2.337ms	50	50	100.00
		aes_alert_reset	12.000s	447.197us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	165.032us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	549.584us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	447.197us	50	50	100.00
V2	stress	aes_stress	30.000s	1.677ms	50	50	100.00
V2	sideload	aes_stress	30.000s	1.677ms	50	50	100.00
		aes_sideload	14.000s	884.434us	50	50	100.00
V2	deinitialization	aes_deinit	1.300m	4.844ms	50	50	100.00
V2	stress_all	aes_stress_all	1.867m	1.658ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	236.399us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	228.387us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	228.387us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	93.471us	5	5	100.00
		aes_csr_rw	3.000s	53.291us	20	20	100.00
		aes_csr_aliasing	5.000s	89.584us	5	5	100.00
		aes_same_csr_outstanding	4.000s	160.703us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	93.471us	5	5	100.00
		aes_csr_rw	3.000s	53.291us	20	20	100.00
		aes_csr_aliasing	5.000s	89.584us	5	5	100.00
		aes_same_csr_outstanding	4.000s	160.703us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	24.000s	1.103ms	50	50	100.00
V2S	fault_inject	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	408.786us	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.825ms	5	5	100.00
		aes_tl_intg_err	6.000s	789.993us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	789.993us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	447.197us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	1.025ms	50	50	100.00
		aes_stress	30.000s	1.677ms	50	50	100.00
		aes_alert_reset	12.000s	447.197us	50	50	100.00
		aes_core_fi	49.000s	10.006ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	284.716us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	80.027us	50	50	100.00
		aes_stress	30.000s	1.677ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	30.000s	1.677ms	50	50	100.00
		aes_sideload	14.000s	884.434us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	80.027us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	80.027us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	80.027us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	80.027us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	80.027us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	30.000s	1.677ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	30.000s	1.677ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.117m	3.913ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.117m	3.913ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.006ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.117m	3.913ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	447.197us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_ctr_fi	6.000s	220.999us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.117m	3.913ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	279	300	93.00
		aes_cipher_fi	50.000s	10.006ms	334	350	95.43
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.917m	19.554ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.53	96.25	99.42	95.69	97.64	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 15 failures.
  - 1.aes_control_fi.101612238274601804575078311488681311622086025579888942607917316893386568946416
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:7318336c-facf-4daa-8a70-154487436b9f
```
  - 52.aes_control_fi.103578574582449183555420606598032010323981476373639995133451983469416790396495
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:87ecffc6-9952-436f-a931-f96f4eac5abe
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 89.aes_cipher_fi.50745967151468789668218926496938166486788426218353791846838178792700272205038
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  Job ID: smart:86bfbba4-f425-4cb8-8ee0-5b5352246685
```
  - 90.aes_cipher_fi.7760204055956696023575891508200511875988163864066517353580975715932555167586
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  Job ID: smart:698cdf36-4222-4379-8d72-ffb648fa9441
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 7.aes_cipher_fi.31505429181256067090185693894608739914001178207400543734196172594920531503546
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015655247 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015655247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_cipher_fi.83028074867877872838988012364417153307414060485696165654770035756772079453392
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028123822 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028123822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.92140396800593305283734041432198489942833349918424035795581149850832540553635
Line 569, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13641263968 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 13641263968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.113177696712621563800266446897254328613490034144414759487523957464012504852108
Line 574, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 433913543 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 433913543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 20.aes_control_fi.15392173866749203186917365175560076765773374191842296836123651620684764715944
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10047911263 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047911263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_control_fi.11254466839556216460838911066891050396748747972237524281883459132111498185285
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014531543 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014531543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.78085441283451111319693204464332607732614329744169829584959461022771974631152
Line 1578, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 822761180 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 822761180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.1648035510357782103492872506028427211696902505486552013318491306843511433949
Line 1607, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 828640365 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 828640365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 13.aes_core_fi.42938473174737673038458395913909847195908360183935226383126075141056899826222
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005751844 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005751844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_core_fi.27539599641023506600443719049229781102569331268855897103550919349502144051755
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035661689 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035661689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.aes_shadow_reg_errors_with_csr_rw.39679359936056027510257036945605997128997606224349879742853870351778812613656
    Line 295, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 49939055 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 49918222 PS)
  UVM_ERROR @  49939055 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @  49939055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```