AES/MASKED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	60.546us	1	1	100.00
V1	smoke	aes_smoke	23.000s	452.085us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	72.838us	5	5	100.00
V1	csr_rw	aes_csr_rw	10.000s	78.634us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	15.000s	988.401us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	182.586us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	14.000s	89.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	10.000s	78.634us	20	20	100.00
		aes_csr_aliasing	5.000s	182.586us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	23.000s	452.085us	50	50	100.00
		aes_config_error	11.000s	103.504us	50	50	100.00
		aes_stress	17.000s	163.408us	50	50	100.00
V2	key_length	aes_smoke	23.000s	452.085us	50	50	100.00
		aes_config_error	11.000s	103.504us	50	50	100.00
		aes_stress	17.000s	163.408us	50	50	100.00
V2	back2back	aes_stress	17.000s	163.408us	50	50	100.00
		aes_b2b	37.000s	404.494us	50	50	100.00
V2	backpressure	aes_stress	17.000s	163.408us	50	50	100.00
V2	multi_message	aes_smoke	23.000s	452.085us	50	50	100.00
		aes_config_error	11.000s	103.504us	50	50	100.00
		aes_stress	17.000s	163.408us	50	50	100.00
		aes_alert_reset	44.000s	2.978ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	623.973us	50	50	100.00
		aes_config_error	11.000s	103.504us	50	50	100.00
		aes_alert_reset	44.000s	2.978ms	50	50	100.00
V2	trigger_clear_test	aes_clear	49.000s	5.258ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	27.000s	1.096ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	44.000s	2.978ms	50	50	100.00
V2	stress	aes_stress	17.000s	163.408us	50	50	100.00
V2	sideload	aes_stress	17.000s	163.408us	50	50	100.00
		aes_sideload	35.000s	1.210ms	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	86.103us	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	2.164ms	10	10	100.00
V2	alert_test	aes_alert_test	19.000s	94.029us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	112.422us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	112.422us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	72.838us	5	5	100.00
		aes_csr_rw	10.000s	78.634us	20	20	100.00
		aes_csr_aliasing	5.000s	182.586us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.252ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	72.838us	5	5	100.00
		aes_csr_rw	10.000s	78.634us	20	20	100.00
		aes_csr_aliasing	5.000s	182.586us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.252ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	21.000s	287.972us	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	181.779us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.295ms	5	5	100.00
		aes_tl_intg_err	9.000s	757.887us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	757.887us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	44.000s	2.978ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	23.000s	452.085us	50	50	100.00
		aes_stress	17.000s	163.408us	50	50	100.00
		aes_alert_reset	44.000s	2.978ms	50	50	100.00
		aes_core_fi	1.450m	10.007ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	83.127us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	76.732us	50	50	100.00
		aes_stress	17.000s	163.408us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	17.000s	163.408us	50	50	100.00
		aes_sideload	35.000s	1.210ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	76.732us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	76.732us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	76.732us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	76.732us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	76.732us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	17.000s	163.408us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	17.000s	163.408us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	3.543ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	3.543ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	35.000s	10.023ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	3.543ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	44.000s	2.978ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_ctr_fi	16.000s	106.398us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	3.543ms	49	50	98.00
		aes_control_fi	47.000s	10.005ms	280	300	93.33
		aes_cipher_fi	35.000s	10.023ms	341	350	97.43
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.633m	65.180ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.52	96.23	99.42	95.76	97.64	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_cipher_fi has 5 failures.
  - 36.aes_cipher_fi.55636989381894975731363442920367979890153756075552916022292712553239793390433
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0dc78710-cb93-4f18-ac08-5dd86db042c4
```
  - 65.aes_cipher_fi.33688846957172888402440343050323923687165280363348604980773611269458369886770
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2fd5f001-c219-49ee-89fa-49e6bb1bd21b
```
  - ... and 3 more failures.
- Test aes_control_fi has 15 failures.
  - 63.aes_control_fi.24605757100268687787673789058446485185046916932092747598400590422377006905624
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  Job ID: smart:8209421e-33ca-4753-b670-4c76ef8b5727
```
  - 75.aes_control_fi.77270009805917491733354020144566638512042248114998623034183461742181917653756
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  Job ID: smart:c9386676-ddb0-41af-a1f9-66f11faf3ee9
```
  - ... and 13 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.81170154583337764427256384409047507948360973910151708519748868297427074812960
Line 888, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2053579500 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2053579500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.87888422871402204568110922362648060950458802516366280042337276010167512925881
Line 604, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4362249901 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4362249901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 15.aes_control_fi.39782188772527514693376518897628331814842792440667963440404431653995134586712
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004786271 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004786271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.aes_control_fi.42020999726691750972000561113365560493496210281663533619899281638743553553069
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012981826 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012981826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 100.aes_cipher_fi.115280495107578113993658427233323733201439498647380051330534260800669251018409
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10037072500 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037072500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 187.aes_cipher_fi.26965232166293605883258121696945157143408499524254946215958974491706486563083
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/187.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10262242036 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10262242036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.37740822776788052501801210607000671628960714825963325077962117214110699476356
Line 603, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 376047122 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 376047122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.42913080479637886970684729056647074488595340463062762931818225964433693786500
Line 1099, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1019974879 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1019974879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 32.aes_core_fi.16625386835060196610443700401529615767717693766750532196105302340218454705325
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005455727 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005455727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.75527019437712734940526192698733716438955732904711281699379511350211046617503
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039720097 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039720097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.51987095547212874361372611073894577772850461930393745223495324101962300024637
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  45322865 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  45322865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 19.aes_same_csr_outstanding.112365395807997863220149074435202169024709002223324272177700362214031848733233
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10252181354 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x8837c584) == 0x0
  UVM_INFO @ 10252181354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 35.aes_fi.68805574856901420058536389856295805671597164097061443405067303271942982074505
    Line 33154, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_fi/latest/run.log
```
  UVM_FATAL @ 912051527 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 912051527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```