f92a5ee77b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 74.358us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 6.217m | 10.009ms | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 9.000s | 613.700us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 85.145us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 7.000s | 69.658us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 6.217m | 10.009ms | 18 | 20 | 90.00 |
| aes_csr_aliasing | 5.000s | 85.145us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 51 | 106 | 48.11 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 9.000s | 142.948us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 9.000s | 142.948us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 74.358us | 5 | 5 | 100.00 |
| aes_csr_rw | 6.217m | 10.009ms | 18 | 20 | 90.00 | ||
| aes_csr_aliasing | 5.000s | 85.145us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 9.000s | 576.527us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 74.358us | 5 | 5 | 100.00 |
| aes_csr_rw | 6.217m | 10.009ms | 18 | 20 | 90.00 | ||
| aes_csr_aliasing | 5.000s | 85.145us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 9.000s | 576.527us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 9.000s | 99.240us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 7.000s | 1.685ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 7.000s | 1.685ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 13.000s | 54.858us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 151 | 1602 | 9.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 3 | 42.86 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 83.99 | 99.38 | 98.15 | 99.87 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.41655702692589933615363382622116663213355498015713528185300349438454967171726
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.34727255236640274277161947902644926592749023659571226721638483952265663935494
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.79600506803732268314527153220308570918626234882556501636506927979825597611049
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.113272648586252498554394955766763305921228128960693393832595587105932612013746
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.29813567823196630862065974579922290047970781091853861189702547923865667254905
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.113997710188734926477287516923454355617054276295930638163822343055024034935730
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.1238581415936578464930511265964007498057058882311347323912517809818036476010
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.97289101806605919343200519905448999864651204134821653626636734792369018300538
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.65322249736286114932502820196977251531124064480077778299537238200294389739526
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.104284235970503292142581990283358631090198258092507390176867905257301441216067
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.97150814774160649642289193700011819233082194110003272069249909042528567367161
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.94303977667047249575175446446353322807925011983692355416980385201753654703962
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.98731350184786305262736236173954786415489049740840557191272196059483165176769
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.76338116151301311369486467235063404150071549585383633469501189092796179995232
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.42142442020816941854587536804700256679899023150139383460234469067690889107068
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.54567560808980890145627021585902975770901718534423371510899207068077813700824
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
2.aes_csr_mem_rw_with_rand_reset.67799344276141311657213830192727863214307483912628445926881941018630674118465
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 117352111 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 117352111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
11.aes_csr_rw.55028388341944127904541362173387410587250580490323745614244173263465928975051
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_csr_rw/latest/run.log
UVM_FATAL @ 10008507966 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xbfd92584) == 0x0
UVM_INFO @ 10008507966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
14.aes_csr_mem_rw_with_rand_reset.52845853254807786000711411052583174300256505941805027091609848543238253699421
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 426488388 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 426488388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) has 1 failures:
18.aes_csr_rw.54036895584877383055878378196192009195547174533584359073708500819137894974429
Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_csr_rw/latest/run.log
xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 8493620 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 8483519 PS)
UVM_ERROR @ 8493620 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
UVM_INFO @ 8493620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---