AES/MASKED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	78.391us	1	1	100.00
V1	smoke	aes_smoke	21.000s	115.921us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	79.304us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	60.646us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.420ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	133.682us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	97.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	60.646us	20	20	100.00
		aes_csr_aliasing	6.000s	133.682us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	21.000s	115.921us	50	50	100.00
		aes_config_error	18.000s	2.295ms	50	50	100.00
		aes_stress	21.000s	413.158us	50	50	100.00
V2	key_length	aes_smoke	21.000s	115.921us	50	50	100.00
		aes_config_error	18.000s	2.295ms	50	50	100.00
		aes_stress	21.000s	413.158us	50	50	100.00
V2	back2back	aes_stress	21.000s	413.158us	50	50	100.00
		aes_b2b	42.000s	820.909us	50	50	100.00
V2	backpressure	aes_stress	21.000s	413.158us	50	50	100.00
V2	multi_message	aes_smoke	21.000s	115.921us	50	50	100.00
		aes_config_error	18.000s	2.295ms	50	50	100.00
		aes_stress	21.000s	413.158us	50	50	100.00
		aes_alert_reset	1.300m	5.459ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	122.391us	50	50	100.00
		aes_config_error	18.000s	2.295ms	50	50	100.00
		aes_alert_reset	1.300m	5.459ms	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	2.047ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	1.151ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.300m	5.459ms	50	50	100.00
V2	stress	aes_stress	21.000s	413.158us	50	50	100.00
V2	sideload	aes_stress	21.000s	413.158us	50	50	100.00
		aes_sideload	42.000s	1.435ms	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	465.936us	50	50	100.00
V2	stress_all	aes_stress_all	3.683m	8.470ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	75.603us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	93.129us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	93.129us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	79.304us	5	5	100.00
		aes_csr_rw	9.000s	60.646us	20	20	100.00
		aes_csr_aliasing	6.000s	133.682us	5	5	100.00
		aes_same_csr_outstanding	8.000s	96.877us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	79.304us	5	5	100.00
		aes_csr_rw	9.000s	60.646us	20	20	100.00
		aes_csr_aliasing	6.000s	133.682us	5	5	100.00
		aes_same_csr_outstanding	8.000s	96.877us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	20.000s	101.580us	50	50	100.00
V2S	fault_inject	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	99.899us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.011ms	5	5	100.00
		aes_tl_intg_err	5.000s	388.995us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	388.995us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.300m	5.459ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	21.000s	115.921us	50	50	100.00
		aes_stress	21.000s	413.158us	50	50	100.00
		aes_alert_reset	1.300m	5.459ms	50	50	100.00
		aes_core_fi	1.317m	10.009ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	77.957us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	88.866us	50	50	100.00
		aes_stress	21.000s	413.158us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	21.000s	413.158us	50	50	100.00
		aes_sideload	42.000s	1.435ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	88.866us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	88.866us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	88.866us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	88.866us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	88.866us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	21.000s	413.158us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	21.000s	413.158us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	19.000s	286.781us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	19.000s	286.781us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.009ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	19.000s	286.781us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.300m	5.459ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_ctr_fi	12.000s	76.538us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	19.000s	286.781us	50	50	100.00
		aes_control_fi	44.000s	10.036ms	276	300	92.00
		aes_cipher_fi	47.000s	10.009ms	344	350	98.29
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.267m	45.044ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.27	98.47	96.12	99.36	95.72	97.72	97.78	99.11	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 16 failures.
  - 45.aes_control_fi.74872973393950188132617968045270923639603813689852647929680028469757258342234
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:b338b65f-7482-41f7-99c8-a8aef9a976d5
```
  - 51.aes_control_fi.31546249695366982127090227493626505596441162406606507798791926589531403985189
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:a33d0b11-5d68-4468-bc82-a633f81dccec
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 1 failures.
  - 218.aes_cipher_fi.82902759263549664199208547317349916301590599792399769103707576105169923176890
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/218.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7b2e56af-d90b-4875-88fd-ba80af2d7120
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 19.aes_control_fi.77342460903647636725393757063075573427519533852160558939598637342891995482358
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014971670 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014971670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_control_fi.92119733020680760549479073163829364456352824321100484128381010440278748613890
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011205027 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011205027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.21073746388354474826629837338500267581615070871929683218374674678968391840334
Line 738, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1275938751 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1275938751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.3504732152773006739786541984067656635188067274196189552434474619071257359802
Line 591, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 531222141 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 531222141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 59.aes_cipher_fi.18376846626281760447207593465249686119825949456645518909005725886504455037168
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018744503 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018744503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_cipher_fi.74485363035297542561869823997307596702397696554754012265188913681996200951943
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009411320 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009411320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 40.aes_core_fi.17576242863107318731650923769670363165850473888749759377398315601330455225453
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008990904 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008990904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.aes_core_fi.70189901776988728059145207279523796548252108991245421386445355559487395727848
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016383561 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016383561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.33475846220624968154701546417022432324853232038178298835142679680082569278034
Line 1557, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3537827027 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3537827027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.53236006467410355056576829033972245746180462905886432119616474428961475766885
Line 1147, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3345585274 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3345585274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.104239063082875918442136565946725586690669763114493961301442059177957855566317
    Line 635, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3353413032 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3353413032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```