AES/MASKED Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	201.024us	1	1	100.00
V1	smoke	aes_smoke	6.000s	91.581us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	73.378us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	186.038us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	2.866ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	2.026ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	71.988us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	186.038us	20	20	100.00
		aes_csr_aliasing	6.000s	2.026ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	91.581us	50	50	100.00
		aes_config_error	14.000s	843.746us	50	50	100.00
		aes_stress	9.000s	1.034ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	91.581us	50	50	100.00
		aes_config_error	14.000s	843.746us	50	50	100.00
		aes_stress	9.000s	1.034ms	50	50	100.00
V2	back2back	aes_stress	9.000s	1.034ms	50	50	100.00
		aes_b2b	39.000s	435.283us	50	50	100.00
V2	backpressure	aes_stress	9.000s	1.034ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	91.581us	50	50	100.00
		aes_config_error	14.000s	843.746us	50	50	100.00
		aes_stress	9.000s	1.034ms	50	50	100.00
		aes_alert_reset	1.483m	7.611ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	67.623us	50	50	100.00
		aes_config_error	14.000s	843.746us	50	50	100.00
		aes_alert_reset	1.483m	7.611ms	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	589.793us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	608.218us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.483m	7.611ms	50	50	100.00
V2	stress	aes_stress	9.000s	1.034ms	50	50	100.00
V2	sideload	aes_stress	9.000s	1.034ms	50	50	100.00
		aes_sideload	48.000s	2.762ms	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	635.395us	50	50	100.00
V2	stress_all	aes_stress_all	12.150m	41.264ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	143.607us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	291.663us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	291.663us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	73.378us	5	5	100.00
		aes_csr_rw	4.000s	186.038us	20	20	100.00
		aes_csr_aliasing	6.000s	2.026ms	5	5	100.00
		aes_same_csr_outstanding	51.000s	10.162ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	73.378us	5	5	100.00
		aes_csr_rw	4.000s	186.038us	20	20	100.00
		aes_csr_aliasing	6.000s	2.026ms	5	5	100.00
		aes_same_csr_outstanding	51.000s	10.162ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	13.000s	687.468us	50	50	100.00
V2S	fault_inject	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	247.164us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	29.000s	6.106ms	5	5	100.00
		aes_tl_intg_err	5.000s	278.727us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	278.727us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.483m	7.611ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	91.581us	50	50	100.00
		aes_stress	9.000s	1.034ms	50	50	100.00
		aes_alert_reset	1.483m	7.611ms	50	50	100.00
		aes_core_fi	31.000s	10.017ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	66.859us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	179.762us	50	50	100.00
		aes_stress	9.000s	1.034ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	1.034ms	50	50	100.00
		aes_sideload	48.000s	2.762ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	179.762us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	179.762us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	179.762us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	179.762us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	179.762us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	1.034ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	1.034ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	47.000s	2.091ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	47.000s	2.091ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.005ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	47.000s	2.091ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.483m	7.611ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_ctr_fi	11.000s	2.225ms	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	47.000s	2.091ms	49	50	98.00
		aes_control_fi	46.000s	10.009ms	278	300	92.67
		aes_cipher_fi	50.000s	10.005ms	338	350	96.57
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.367m	27.362ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.55	96.32	99.43	95.78	97.72	97.78	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 6 failures.
  - 3.aes_cipher_fi.40203182470072510173102883241929737856035911517791174442829683652084879218075
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d8b8bc6d-9f47-457f-a00b-9e00ba909b17
```
  - 105.aes_cipher_fi.28441803226491428553200146132350945372482906633712605495428963790491565950405
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f8e04fb1-9874-4611-ac5b-cb0d21686068
```
  - ... and 4 more failures.
- Test aes_control_fi has 16 failures.
  - 5.aes_control_fi.70748834091379844683806647475546607164723989870728444091198536065018848979740
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:5a40a4d2-5574-4bd9-89de-eb05b07dfdda
```
  - 41.aes_control_fi.66419566388267675527180376142556063221030242540598623813220096610480566074486
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  Job ID: smart:19a660ce-24de-462a-997e-f1f22f5ac445
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 9.aes_cipher_fi.7658490965970947834656345093673717783287104623072402947449829954650715852599
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10024618130 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024618130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 112.aes_cipher_fi.3196044817431666432212089790491864092089675969905019846558920863665901964795
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/112.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012291903 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012291903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 56.aes_control_fi.86013801061026153441745766603033313391463510239498766461562219265215131582618
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012282613 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012282613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 90.aes_control_fi.83837025183853878637583395292925874108301368666770045547267835255983968640756
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006478847 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006478847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.40746520093430827913277883338122503508092080540738208383843780536347391326019
Line 652, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 448001738 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 448001738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.12809387386981396845634112354946876038161614586333290610627541362601728988665
Line 1507, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2362147633 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2362147633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.87556127422337855196661168265253336837582274310913021697788721344271773819764
Line 732, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4218349252 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4218349252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.50921608461533796146655010235311273539064452567880033719248203989566634017472
Line 815, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 352592206 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 352592206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 31.aes_core_fi.96155587170921023132222175718029266539207932409763283930843432320437694099782
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008395703 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008395703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_core_fi.92488124647459285180439387435780265445299486145633227162266847231057263064083
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016741965 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016741965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 6.aes_same_csr_outstanding.38421224372839482209373958096572215761406371938126274108337475110207978422046
    Line 298, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10161888818 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x9bcbdc84) == 0x0
  UVM_INFO @ 10161888818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 44.aes_fi.19116332470866560025648323576725617246028856805991157333498781679620283175285
    Line 3330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 20375032 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 20355032 PS)
  UVM_ERROR @  20375032 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  20375032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```