AES/MASKED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	108.986us	1	1	100.00
V1	smoke	aes_smoke	17.000s	169.818us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	90.768us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	178.528us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	2.430ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	327.364us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	262.780us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	178.528us	20	20	100.00
		aes_csr_aliasing	5.000s	327.364us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	17.000s	169.818us	50	50	100.00
		aes_config_error	21.000s	471.918us	50	50	100.00
		aes_stress	30.000s	1.839ms	50	50	100.00
V2	key_length	aes_smoke	17.000s	169.818us	50	50	100.00
		aes_config_error	21.000s	471.918us	50	50	100.00
		aes_stress	30.000s	1.839ms	50	50	100.00
V2	back2back	aes_stress	30.000s	1.839ms	50	50	100.00
		aes_b2b	1.117m	876.158us	50	50	100.00
V2	backpressure	aes_stress	30.000s	1.839ms	50	50	100.00
V2	multi_message	aes_smoke	17.000s	169.818us	50	50	100.00
		aes_config_error	21.000s	471.918us	50	50	100.00
		aes_stress	30.000s	1.839ms	50	50	100.00
		aes_alert_reset	54.000s	4.241ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	74.666us	50	50	100.00
		aes_config_error	21.000s	471.918us	50	50	100.00
		aes_alert_reset	54.000s	4.241ms	50	50	100.00
V2	trigger_clear_test	aes_clear	36.000s	1.990ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	299.823us	1	1	100.00
V2	reset_recovery	aes_alert_reset	54.000s	4.241ms	50	50	100.00
V2	stress	aes_stress	30.000s	1.839ms	50	50	100.00
V2	sideload	aes_stress	30.000s	1.839ms	50	50	100.00
		aes_sideload	46.000s	1.801ms	50	50	100.00
V2	deinitialization	aes_deinit	20.000s	664.935us	50	50	100.00
V2	stress_all	aes_stress_all	1.100m	2.313ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	74.878us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	156.196us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	156.196us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	90.768us	5	5	100.00
		aes_csr_rw	3.000s	178.528us	20	20	100.00
		aes_csr_aliasing	5.000s	327.364us	5	5	100.00
		aes_same_csr_outstanding	4.000s	134.162us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	90.768us	5	5	100.00
		aes_csr_rw	3.000s	178.528us	20	20	100.00
		aes_csr_aliasing	5.000s	327.364us	5	5	100.00
		aes_same_csr_outstanding	4.000s	134.162us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.650m	6.402ms	49	50	98.00
V2S	fault_inject	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	241.166us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	17.000s	1.082ms	5	5	100.00
		aes_tl_intg_err	6.000s	275.795us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	275.795us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	54.000s	4.241ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	17.000s	169.818us	50	50	100.00
		aes_stress	30.000s	1.839ms	50	50	100.00
		aes_alert_reset	54.000s	4.241ms	50	50	100.00
		aes_core_fi	1.450m	10.005ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	58.733us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	82.651us	50	50	100.00
		aes_stress	30.000s	1.839ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	30.000s	1.839ms	50	50	100.00
		aes_sideload	46.000s	1.801ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	82.651us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	82.651us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	82.651us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	82.651us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	82.651us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	30.000s	1.839ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	30.000s	1.839ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	1.263ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	1.263ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.019ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	1.263ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	54.000s	4.241ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_ctr_fi	13.000s	74.498us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	1.263ms	49	50	98.00
		aes_control_fi	47.000s	10.011ms	283	300	94.33
		aes_cipher_fi	50.000s	10.019ms	338	350	96.57
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.600m	22.202ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.42	95.78	97.72	98.52	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 13 failures.
  - 18.aes_control_fi.62362216111983258172252651636507635976073394884841254288733656247127148171496
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:121c7629-2ef2-46dd-a4c4-cb6ace5ec557
```
  - 31.aes_control_fi.32119383760566166919105840351001084897217230777711884179930235083193843832441
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job ID: smart:389f333a-9cae-4336-9af0-4bc0be889d27
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 5 failures.
  - 39.aes_cipher_fi.107416340279805979464344160396443885745840200030242737978097153298474635782704
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cb911247-88ce-401c-9dee-98643e8f5536
```
  - 55.aes_cipher_fi.59033277021731034852402260805124024565171980257573862681971449956426365054256
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d7ea2c2e-094b-413b-9462-b03b97b39c14
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 22.aes_cipher_fi.106906901000316951307541220643982602528276861421809873527542490087468609462703
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10024467340 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024467340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 114.aes_cipher_fi.90457821855975520407650299531840475505892090003523791714701005795015033999685
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018935665 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018935665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.8071697968277985694052128393714299125516726886831775563335374151629870497400
Line 1731, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9440013864 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9440013864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.109611184097245807009143813375704407589128508032114172644123492054110689176198
Line 952, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 836418693 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 836418693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 24.aes_control_fi.14892728706255459406875820341886212348249195698318891460214245225304203754122
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008597801 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008597801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_control_fi.28260194268095857626865733250800189235380125155293290247443189110178216219212
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004980217 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004980217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 27.aes_core_fi.34214414949906933231173192297360251263789152403651713663432746181569269633145
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005349412 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005349412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.102897925597864141854645666983276729284943439856659893581996582604709823442889
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012936015 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012936015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.32187260723444155862415930855531263635323811832129373773599887743846758189447
Line 929, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 416924017 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 416924017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.108359883295068493803985096330704809297677947894178850226230602911191175538576
Line 760, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1271894060 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1271894060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.30343354619589626085190836414771282366752380422843943546843189300122759203308
    Line 350, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35292122 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  35292122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 27.aes_reseed.69370725622894343935559525972894715229154078602179157020129374529659179100775
    Line 1301, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_reseed/latest/run.log
```
  UVM_FATAL @ 216689288 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 216689288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 36.aes_fi.109331658721571672985923998005106106983922584756491281565887544637894084749464
    Line 6458, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_fi/latest/run.log
```
  UVM_FATAL @  81620520 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  81620520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```