AES/MASKED Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	373.897us	1	1	100.00
V1	smoke	aes_smoke	10.000s	83.304us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	185.869us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.600m	10.017ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	323.172us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	812.454us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	271.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.600m	10.017ms	19	20	95.00
		aes_csr_aliasing	6.000s	812.454us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	10.000s	83.304us	50	50	100.00
		aes_config_error	39.000s	1.274ms	50	50	100.00
		aes_stress	19.000s	1.708ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	83.304us	50	50	100.00
		aes_config_error	39.000s	1.274ms	50	50	100.00
		aes_stress	19.000s	1.708ms	50	50	100.00
V2	back2back	aes_stress	19.000s	1.708ms	50	50	100.00
		aes_b2b	45.000s	541.587us	50	50	100.00
V2	backpressure	aes_stress	19.000s	1.708ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	83.304us	50	50	100.00
		aes_config_error	39.000s	1.274ms	50	50	100.00
		aes_stress	19.000s	1.708ms	50	50	100.00
		aes_alert_reset	31.000s	1.050ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	75.248us	50	50	100.00
		aes_config_error	39.000s	1.274ms	50	50	100.00
		aes_alert_reset	31.000s	1.050ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	247.637us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	224.847us	1	1	100.00
V2	reset_recovery	aes_alert_reset	31.000s	1.050ms	50	50	100.00
V2	stress	aes_stress	19.000s	1.708ms	50	50	100.00
V2	sideload	aes_stress	19.000s	1.708ms	50	50	100.00
		aes_sideload	36.000s	1.108ms	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	102.439us	50	50	100.00
V2	stress_all	aes_stress_all	5.833m	41.133ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	58.482us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	259.899us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	259.899us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	185.869us	5	5	100.00
		aes_csr_rw	1.600m	10.017ms	19	20	95.00
		aes_csr_aliasing	6.000s	812.454us	5	5	100.00
		aes_same_csr_outstanding	3.233m	10.036ms	18	20	90.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	185.869us	5	5	100.00
		aes_csr_rw	1.600m	10.017ms	19	20	95.00
		aes_csr_aliasing	6.000s	812.454us	5	5	100.00
		aes_same_csr_outstanding	3.233m	10.036ms	18	20	90.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	27.000s	851.228us	50	50	100.00
V2S	fault_inject	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	412.318us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	971.690us	5	5	100.00
		aes_tl_intg_err	5.000s	226.261us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	226.261us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	31.000s	1.050ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	83.304us	50	50	100.00
		aes_stress	19.000s	1.708ms	50	50	100.00
		aes_alert_reset	31.000s	1.050ms	50	50	100.00
		aes_core_fi	26.000s	10.014ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	247.778us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	101.967us	50	50	100.00
		aes_stress	19.000s	1.708ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	1.708ms	50	50	100.00
		aes_sideload	36.000s	1.108ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	101.967us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	101.967us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	101.967us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	101.967us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	101.967us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	1.708ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	1.708ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	20.000s	160.960us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	20.000s	160.960us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	40.000s	10.008ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	20.000s	160.960us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	31.000s	1.050ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_ctr_fi	13.000s	86.795us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	20.000s	160.960us	50	50	100.00
		aes_control_fi	47.000s	10.008ms	278	300	92.67
		aes_cipher_fi	40.000s	10.008ms	337	350	96.29
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.817m	119.322ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.56	96.34	99.44	95.65	97.72	97.78	99.11	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 15 failures.
  - 7.aes_control_fi.61650187435161402233224566936565300865111311151717437129156591105387508887803
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:c5fcdafe-cc06-4c20-a979-fdde3a182653
```
  - 38.aes_control_fi.80618993194477429392761108214410558958500688869792135848595411127532835255341
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  Job ID: smart:c77a74db-0a34-460a-9523-f07868eee635
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 7 failures.
  - 100.aes_cipher_fi.11550614250831823373014151385521095767552460975560367164015155781838364717301
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  Job ID: smart:da4413ce-ba09-4f2b-9466-ed25b18854c9
```
  - 131.aes_cipher_fi.3642049644270354086974219485355142089801559134221593832037055041681164005565
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/131.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5cf5d4d7-9f85-4669-99af-6edd6605b651
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.92071049825472486610817128408226823299714778195158354355570898655238334515203
Line 925, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 119321531267 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 119321531267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.110456918915020887268346284857343333654408629681058711886861246050005090152550
Line 1393, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2100485559 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2100485559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 27.aes_control_fi.68910606564849123945951239297744782360110957894513093695180106114146736228286
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013978163 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013978163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 88.aes_control_fi.109768064694691103561219885221533403365305329270263502715491138343777317379563
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030093409 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030093409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 51.aes_cipher_fi.13816615053854746871835630676342664758779227877731255259850410627207669948215
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022679188 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022679188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_cipher_fi.9743189802124775166424163870403492752603208649911777964204992918439005105718
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008864480 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008864480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 3 failures:
- Test aes_csr_rw has 1 failures.
  - 5.aes_csr_rw.13067226795601961248210729470064186473276108734993357778312194893405695678097
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10016776865 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xf6db1a84) == 0x0
  UVM_INFO @ 10016776865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_same_csr_outstanding has 2 failures.
  - 11.aes_same_csr_outstanding.23570707305505423965434925968432701813401806694973650010776992450979687172238
    Line 301, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10036478994 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x17032884) == 0x0
  UVM_INFO @ 10036478994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.aes_same_csr_outstanding.95398925427625362893725101239619116570236852646343411098569166722384709023383
    Line 297, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10065553892 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x8bd5f584) == 0x0
  UVM_INFO @ 10065553892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.64282637429746339772114125059031107916860612376825910692841791399186231436831
Line 656, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3342734088 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3342734088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.75595394311002549908109896979197637567534088972949448994941921715479949063202
Line 1630, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3309422803 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3309422803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 48.aes_core_fi.36263141165057766062892396436025794652100086785126843363440392515608527420349
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10050892640 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10050892640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_core_fi.15961131000183468012356272948975442617386991882656747433282117956119431790603
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014025185 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014025185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.7398111393289938065672542704479904525956696449186982856708832472735796614967
    Line 678, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 659110470 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 659110470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```