AES/MASKED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	60.146us	1	1	100.00
V1	smoke	aes_smoke	14.000s	933.357us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.615us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	68.728us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	528.154us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	343.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	100.835us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	68.728us	20	20	100.00
		aes_csr_aliasing	6.000s	343.298us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	933.357us	50	50	100.00
		aes_config_error	9.000s	471.662us	50	50	100.00
		aes_stress	13.000s	320.256us	50	50	100.00
V2	key_length	aes_smoke	14.000s	933.357us	50	50	100.00
		aes_config_error	9.000s	471.662us	50	50	100.00
		aes_stress	13.000s	320.256us	50	50	100.00
V2	back2back	aes_stress	13.000s	320.256us	50	50	100.00
		aes_b2b	47.000s	602.906us	50	50	100.00
V2	backpressure	aes_stress	13.000s	320.256us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	933.357us	50	50	100.00
		aes_config_error	9.000s	471.662us	50	50	100.00
		aes_stress	13.000s	320.256us	50	50	100.00
		aes_alert_reset	10.000s	224.727us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	146.155us	50	50	100.00
		aes_config_error	9.000s	471.662us	50	50	100.00
		aes_alert_reset	10.000s	224.727us	50	50	100.00
V2	trigger_clear_test	aes_clear	22.000s	1.137ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	352.631us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	224.727us	50	50	100.00
V2	stress	aes_stress	13.000s	320.256us	50	50	100.00
V2	sideload	aes_stress	13.000s	320.256us	50	50	100.00
		aes_sideload	40.000s	2.802ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	143.752us	50	50	100.00
V2	stress_all	aes_stress_all	2.433m	5.235ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	411.004us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	2.115ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	2.115ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.615us	5	5	100.00
		aes_csr_rw	3.000s	68.728us	20	20	100.00
		aes_csr_aliasing	6.000s	343.298us	5	5	100.00
		aes_same_csr_outstanding	4.000s	62.591us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.615us	5	5	100.00
		aes_csr_rw	3.000s	68.728us	20	20	100.00
		aes_csr_aliasing	6.000s	343.298us	5	5	100.00
		aes_same_csr_outstanding	4.000s	62.591us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	6.150m	13.132ms	50	50	100.00
V2S	fault_inject	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	407.247us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.621ms	5	5	100.00
		aes_tl_intg_err	5.000s	336.508us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	336.508us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	224.727us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	933.357us	50	50	100.00
		aes_stress	13.000s	320.256us	50	50	100.00
		aes_alert_reset	10.000s	224.727us	50	50	100.00
		aes_core_fi	40.000s	10.013ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	82.760us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	53.249us	50	50	100.00
		aes_stress	13.000s	320.256us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	320.256us	50	50	100.00
		aes_sideload	40.000s	2.802ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	53.249us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	53.249us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	53.249us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	53.249us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	53.249us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	320.256us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	320.256us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.700m	3.666ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.700m	3.666ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.700m	3.666ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	224.727us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_ctr_fi	10.000s	355.029us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.700m	3.666ms	49	50	98.00
		aes_control_fi	53.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	332	350	94.86
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.333m	8.484ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.28	99.44	95.80	97.64	99.26	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 11 failures.
  - 27.aes_control_fi.79914325141854673682442239703847200961839624257795965022669901790966332810028
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:0ed02926-e696-44bc-9d43-fe6080468163
```
  - 48.aes_control_fi.34237031061013369708426190536873398554191968108234683837462579486677000779646
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job ID: smart:d2712181-f8af-4b3b-887e-1e2b4f4a355f
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 7 failures.
  - 32.aes_cipher_fi.40700996928173663663495342405571629536784594859128978151144767417490143773279
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e86644b6-9d2c-4db5-8346-934a97c39be5
```
  - 54.aes_cipher_fi.44763249741867572957176329124993766464373908361544005550465280133179443110966
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  Job ID: smart:fdbeebbf-22fe-4b47-b193-deef4aba5aa2
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 16.aes_cipher_fi.33014401611344063183005065816419638731058448641486418941528947454954865331887
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10192651238 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10192651238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_cipher_fi.64369756163363624644581616810620704685867669613729761848132099385432324438254
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011960916 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011960916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 8.aes_control_fi.60104960793059665904954484333764665729949923410392143690260939132425444690185
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004745652 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004745652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 105.aes_control_fi.46675533574319070766254267957782872969728709078414948548618628815754678677930
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004412151 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004412151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.8502917316593602477915422781119478957770052191384781834632182064502248042297
Line 1272, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8484372736 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8484372736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.47674606871981052591441047002132154996725069939251038791719834732768928064920
Line 739, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1226195997 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1226195997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

7.aes_stress_all_with_rand_reset.36638823491933427073610526185755151021571586876324479387477264409927407971942
Line 642, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 401815112 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 401815112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.105179325339117204081952819470998858904889921686165351316589097274938089763496
Line 927, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 604925782 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 604925782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 25.aes_core_fi.107307745233759737916748256437390161740299154405778056363228976176588409941019
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013282453 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013282453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.aes_core_fi.69001475430114378194336287701847932290997995853749797795521204389690127224967
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025257147 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025257147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 37.aes_fi.4306036342759194590669710601916314320554371894169703959245531969752430850491
    Line 38274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_fi/latest/run.log
```
  UVM_FATAL @ 398911574 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 398911574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```