AES/MASKED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	97.983us	1	1	100.00
V1	smoke	aes_smoke	12.000s	373.985us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	86.954us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	60.766us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	529.249us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	132.846us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	150.780us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	60.766us	20	20	100.00
		aes_csr_aliasing	5.000s	132.846us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	373.985us	50	50	100.00
		aes_config_error	16.000s	434.139us	50	50	100.00
		aes_stress	1.150m	6.923ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	373.985us	50	50	100.00
		aes_config_error	16.000s	434.139us	50	50	100.00
		aes_stress	1.150m	6.923ms	50	50	100.00
V2	back2back	aes_stress	1.150m	6.923ms	50	50	100.00
		aes_b2b	40.000s	497.410us	50	50	100.00
V2	backpressure	aes_stress	1.150m	6.923ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	373.985us	50	50	100.00
		aes_config_error	16.000s	434.139us	50	50	100.00
		aes_stress	1.150m	6.923ms	50	50	100.00
		aes_alert_reset	13.000s	1.118ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	280.132us	50	50	100.00
		aes_config_error	16.000s	434.139us	50	50	100.00
		aes_alert_reset	13.000s	1.118ms	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	2.799ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	611.072us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	1.118ms	50	50	100.00
V2	stress	aes_stress	1.150m	6.923ms	50	50	100.00
V2	sideload	aes_stress	1.150m	6.923ms	50	50	100.00
		aes_sideload	42.000s	2.541ms	50	50	100.00
V2	deinitialization	aes_deinit	2.250m	4.537ms	50	50	100.00
V2	stress_all	aes_stress_all	4.350m	8.774ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	96.438us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	514.190us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	514.190us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	86.954us	5	5	100.00
		aes_csr_rw	3.000s	60.766us	20	20	100.00
		aes_csr_aliasing	5.000s	132.846us	5	5	100.00
		aes_same_csr_outstanding	4.000s	191.873us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	86.954us	5	5	100.00
		aes_csr_rw	3.000s	60.766us	20	20	100.00
		aes_csr_aliasing	5.000s	132.846us	5	5	100.00
		aes_same_csr_outstanding	4.000s	191.873us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	48.000s	1.631ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	82.936us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	3.216ms	5	5	100.00
		aes_tl_intg_err	5.000s	379.520us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	379.520us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	1.118ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	373.985us	50	50	100.00
		aes_stress	1.150m	6.923ms	50	50	100.00
		aes_alert_reset	13.000s	1.118ms	50	50	100.00
		aes_core_fi	15.000s	698.337us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	76.471us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	64.240us	50	50	100.00
		aes_stress	1.150m	6.923ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.150m	6.923ms	50	50	100.00
		aes_sideload	42.000s	2.541ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	64.240us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	64.240us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	64.240us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	64.240us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	64.240us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.150m	6.923ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.150m	6.923ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	239.437us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	239.437us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	239.437us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	1.118ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_ctr_fi	19.000s	83.732us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	239.437us	50	50	100.00
		aes_control_fi	48.000s	10.005ms	280	300	93.33
		aes_cipher_fi	48.000s	10.005ms	336	350	96.00
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.600m	7.041ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.29	98.49	96.21	99.38	95.74	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_cipher_fi has 13 failures.
  - 2.aes_cipher_fi.112223374454482336363388337060924084515500114472049472885930360512712776986151
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f54ef1e3-7bea-4aad-bc24-2454926f5b33
```
  - 6.aes_cipher_fi.18929704472536050197857622398869081505165560272936874671014934366496884218792
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:935b84f8-78c3-4091-ba9c-cdee4f7b9012
```
  - ... and 11 more failures.
- Test aes_control_fi has 14 failures.
  - 7.aes_control_fi.95425312233955703798776686753122700221411723151279986957676525190783095930450
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:cc0f7ce6-fb4a-443f-abd6-b72c74b20e38
```
  - 39.aes_control_fi.90278567035692407598018941728449612329602546313260568541244579970498246221785
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:d1fb0e12-9b2f-404f-853f-5e3fd18434d4
```
  - ... and 12 more failures.
- Test aes_ctr_fi has 1 failures.
  - 47.aes_ctr_fi.47274056698223268260475260359255063055831675306737862935085232302987620124400
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_ctr_fi/latest/run.log
```
  Job ID: smart:d364618b-39fd-4959-9a3d-919416e3568e
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.47993717224094028036133008574636828241666625109876732304398064483849090929104
Line 406, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 619040723 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 619040723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.78860205489228181065367845949755838422699007283198725620553796911182014558735
Line 1448, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2607152403 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2607152403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 41.aes_control_fi.94881734385823078957527322201181685887450243300784659865546033243722087937571
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010695434 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010695434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 132.aes_control_fi.15960721639144630623044593041882714390913739041155427546029098923739359674717
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/132.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005412213 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005412213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.30340781623583240936640387827096456961535321478556244438419302044248982898423
Line 1248, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2382022965 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2382022965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.31218661816170232154568844270903376273506456870436078211043200875428855574373
Line 1371, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1521983005 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1521983005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.91986129717176487146603677265371308532435120164858840745704697861827734628954
    Line 212617, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 1180129436 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 1180109436 PS)
  UVM_ERROR @ 1180129436 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 1180129436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 75.aes_cipher_fi.12642264980876566061578762801301506488949763484641419671922377782607591681834
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004622602 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004622602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```