AES/MASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	100.944us	1	1	100.00
V1	smoke	aes_smoke	16.000s	553.268us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	203.905us	5	5	100.00
V1	csr_rw	aes_csr_rw	18.000s	69.895us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	2.933ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	695.421us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	61.298us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	18.000s	69.895us	20	20	100.00
		aes_csr_aliasing	4.000s	695.421us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	16.000s	553.268us	50	50	100.00
		aes_config_error	20.000s	147.620us	50	50	100.00
		aes_stress	25.000s	2.219ms	50	50	100.00
V2	key_length	aes_smoke	16.000s	553.268us	50	50	100.00
		aes_config_error	20.000s	147.620us	50	50	100.00
		aes_stress	25.000s	2.219ms	50	50	100.00
V2	back2back	aes_stress	25.000s	2.219ms	50	50	100.00
		aes_b2b	33.000s	634.014us	50	50	100.00
V2	backpressure	aes_stress	25.000s	2.219ms	50	50	100.00
V2	multi_message	aes_smoke	16.000s	553.268us	50	50	100.00
		aes_config_error	20.000s	147.620us	50	50	100.00
		aes_stress	25.000s	2.219ms	50	50	100.00
		aes_alert_reset	30.000s	1.155ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	60.188us	50	50	100.00
		aes_config_error	20.000s	147.620us	50	50	100.00
		aes_alert_reset	30.000s	1.155ms	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	521.731us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.180ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	30.000s	1.155ms	50	50	100.00
V2	stress	aes_stress	25.000s	2.219ms	50	50	100.00
V2	sideload	aes_stress	25.000s	2.219ms	50	50	100.00
		aes_sideload	18.000s	352.527us	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	763.237us	50	50	100.00
V2	stress_all	aes_stress_all	1.383m	1.179ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	55.233us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	161.967us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	161.967us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	203.905us	5	5	100.00
		aes_csr_rw	18.000s	69.895us	20	20	100.00
		aes_csr_aliasing	4.000s	695.421us	5	5	100.00
		aes_same_csr_outstanding	20.000s	92.926us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	203.905us	5	5	100.00
		aes_csr_rw	18.000s	69.895us	20	20	100.00
		aes_csr_aliasing	4.000s	695.421us	5	5	100.00
		aes_same_csr_outstanding	20.000s	92.926us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	36.000s	1.552ms	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	63.775us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	27.000s	3.033ms	5	5	100.00
		aes_tl_intg_err	8.000s	191.456us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	191.456us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	30.000s	1.155ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	553.268us	50	50	100.00
		aes_stress	25.000s	2.219ms	50	50	100.00
		aes_alert_reset	30.000s	1.155ms	50	50	100.00
		aes_core_fi	1.417m	10.013ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	103.846us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	53.345us	50	50	100.00
		aes_stress	25.000s	2.219ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	25.000s	2.219ms	50	50	100.00
		aes_sideload	18.000s	352.527us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	53.345us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	53.345us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	53.345us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	53.345us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	53.345us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	25.000s	2.219ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	25.000s	2.219ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	224.763us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	224.763us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.023ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	224.763us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	30.000s	1.155ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_ctr_fi	23.000s	68.433us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	224.763us	50	50	100.00
		aes_control_fi	33.000s	10.013ms	280	300	93.33
		aes_cipher_fi	46.000s	10.023ms	339	350	96.86
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.583m	29.793ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.30	99.42	95.74	97.64	97.78	99.11	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_ctr_fi has 1 failures.
  - 16.aes_ctr_fi.107110862335542271808834035025922812654444181640437389348906884494176732627054
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_ctr_fi/latest/run.log
```
  Job ID: smart:bd4c6e67-f472-442e-bc9c-be62c25fb1a0
```
- Test aes_control_fi has 15 failures.
  - 49.aes_control_fi.19629330993695071336428710303046099383257024269405560808344384789518958588889
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job ID: smart:b8779130-d703-43c3-9ec3-a6e0a1979817
```
  - 74.aes_control_fi.34246445830507445755677356501057230571158644243646533671356459686501742183224
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  Job ID: smart:902a6b77-7454-409a-82b4-24977beff6fc
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 71.aes_cipher_fi.80552040114471347306410971654541940561190750512731866538399514752908281399895
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c7713ecb-88f8-405a-9ce2-875a4f545063
```
  - 161.aes_cipher_fi.74805701244861098777962484755435697026760793434027970892047468944707179963637
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/161.aes_cipher_fi/latest/run.log
```
  Job ID: smart:807528d1-9552-4a3a-a6cf-dcfa24e495cf
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.99436481979738489008238887164166403710128603195936776208507255660569178153508
Line 1131, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 980798489 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 980798489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.101451600602343819533939164841031910555932637159352809357165387153437827630710
Line 1531, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1511376559 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1511376559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 63.aes_cipher_fi.26986417848736897675609728446616218410394688559736727942551692948290877984332
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010323871 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010323871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 82.aes_cipher_fi.14535498292876695724989219466268017147625981001399239684277903115570875400092
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10024190433 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024190433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 1.aes_core_fi.44289163674739429513194335086697074340006051116834291511502067871924887329579
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009981811 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009981811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_core_fi.53442727783526177242910369430369089996068240758393451080335254266946469016364
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006311085 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006311085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 29.aes_control_fi.46052334452066976192078513025267653005391386845503671940189343531504004383217
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027629054 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027629054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_control_fi.96819611525877956102657968046611067043423764287527037882557009910619165120092
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010814640 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010814640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.35103188604089063558812702020180077947727856394651632760689221717237838500944
    Line 1388, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6512412476 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6512412476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.114042307264019020088471926233622779384452957479551786086474049711138757915576
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111971595 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111971595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```