AES/MASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 3.000s 100.944us 1 1 100.00
V1 smoke aes_smoke 16.000s 553.268us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 8.000s 203.905us 5 5 100.00
V1 csr_rw aes_csr_rw 18.000s 69.895us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 12.000s 2.933ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 4.000s 695.421us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 8.000s 61.298us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 18.000s 69.895us 20 20 100.00
aes_csr_aliasing 4.000s 695.421us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 16.000s 553.268us 50 50 100.00
aes_config_error 20.000s 147.620us 50 50 100.00
aes_stress 25.000s 2.219ms 50 50 100.00
V2 key_length aes_smoke 16.000s 553.268us 50 50 100.00
aes_config_error 20.000s 147.620us 50 50 100.00
aes_stress 25.000s 2.219ms 50 50 100.00
V2 back2back aes_stress 25.000s 2.219ms 50 50 100.00
aes_b2b 33.000s 634.014us 50 50 100.00
V2 backpressure aes_stress 25.000s 2.219ms 50 50 100.00
V2 multi_message aes_smoke 16.000s 553.268us 50 50 100.00
aes_config_error 20.000s 147.620us 50 50 100.00
aes_stress 25.000s 2.219ms 50 50 100.00
aes_alert_reset 30.000s 1.155ms 50 50 100.00
V2 failure_test aes_man_cfg_err 14.000s 60.188us 50 50 100.00
aes_config_error 20.000s 147.620us 50 50 100.00
aes_alert_reset 30.000s 1.155ms 50 50 100.00
V2 trigger_clear_test aes_clear 18.000s 521.731us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 12.000s 1.180ms 1 1 100.00
V2 reset_recovery aes_alert_reset 30.000s 1.155ms 50 50 100.00
V2 stress aes_stress 25.000s 2.219ms 50 50 100.00
V2 sideload aes_stress 25.000s 2.219ms 50 50 100.00
aes_sideload 18.000s 352.527us 50 50 100.00
V2 deinitialization aes_deinit 25.000s 763.237us 50 50 100.00
V2 stress_all aes_stress_all 1.383m 1.179ms 10 10 100.00
V2 alert_test aes_alert_test 18.000s 55.233us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 14.000s 161.967us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 14.000s 161.967us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 8.000s 203.905us 5 5 100.00
aes_csr_rw 18.000s 69.895us 20 20 100.00
aes_csr_aliasing 4.000s 695.421us 5 5 100.00
aes_same_csr_outstanding 20.000s 92.926us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 8.000s 203.905us 5 5 100.00
aes_csr_rw 18.000s 69.895us 20 20 100.00
aes_csr_aliasing 4.000s 695.421us 5 5 100.00
aes_same_csr_outstanding 20.000s 92.926us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 36.000s 1.552ms 50 50 100.00
V2S fault_inject aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
V2S shadow_reg_update_error aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 8.000s 63.775us 20 20 100.00
V2S tl_intg_err aes_sec_cm 27.000s 3.033ms 5 5 100.00
aes_tl_intg_err 8.000s 191.456us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 8.000s 191.456us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 30.000s 1.155ms 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 16.000s 553.268us 50 50 100.00
aes_stress 25.000s 2.219ms 50 50 100.00
aes_alert_reset 30.000s 1.155ms 50 50 100.00
aes_core_fi 1.417m 10.013ms 65 70 92.86
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 7.000s 103.846us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 18.000s 53.345us 50 50 100.00
aes_stress 25.000s 2.219ms 50 50 100.00
V2S sec_cm_key_sideload aes_stress 25.000s 2.219ms 50 50 100.00
aes_sideload 18.000s 352.527us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 18.000s 53.345us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 18.000s 53.345us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 18.000s 53.345us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 18.000s 53.345us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 18.000s 53.345us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 25.000s 2.219ms 50 50 100.00
V2S sec_cm_key_masking aes_stress 25.000s 2.219ms 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 15.000s 224.763us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_cipher_fsm_sparse aes_fi 15.000s 224.763us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 46.000s 10.023ms 339 350 96.86
V2S sec_cm_ctr_fsm_sparse aes_fi 15.000s 224.763us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_ctrl_sparse aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 30.000s 1.155ms 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_ctr_fi 23.000s 68.433us 49 50 98.00
V2S sec_cm_data_reg_local_esc aes_fi 15.000s 224.763us 50 50 100.00
aes_control_fi 33.000s 10.013ms 280 300 93.33
aes_cipher_fi 46.000s 10.023ms 339 350 96.86
V2S TOTAL 948 985 96.24
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 15.583m 29.793ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1555 1602 97.07

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 11 11 7 63.64
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.34 98.54 96.30 99.42 95.74 97.64 97.78 99.11 96.61

Failure Buckets

Past Results