AES/MASKED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	14.000s	70.593us	1	1	100.00
V1	smoke	aes_smoke	19.000s	86.651us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	99.049us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	63.705us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.450ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	273.042us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	128.157us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	63.705us	20	20	100.00
		aes_csr_aliasing	5.000s	273.042us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	19.000s	86.651us	50	50	100.00
		aes_config_error	36.000s	1.316ms	50	50	100.00
		aes_stress	28.000s	900.760us	50	50	100.00
V2	key_length	aes_smoke	19.000s	86.651us	50	50	100.00
		aes_config_error	36.000s	1.316ms	50	50	100.00
		aes_stress	28.000s	900.760us	50	50	100.00
V2	back2back	aes_stress	28.000s	900.760us	50	50	100.00
		aes_b2b	54.000s	1.348ms	50	50	100.00
V2	backpressure	aes_stress	28.000s	900.760us	50	50	100.00
V2	multi_message	aes_smoke	19.000s	86.651us	50	50	100.00
		aes_config_error	36.000s	1.316ms	50	50	100.00
		aes_stress	28.000s	900.760us	50	50	100.00
		aes_alert_reset	15.000s	93.856us	50	50	100.00
V2	failure_test	aes_man_cfg_err	19.000s	70.114us	50	50	100.00
		aes_config_error	36.000s	1.316ms	50	50	100.00
		aes_alert_reset	15.000s	93.856us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.033m	2.924ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	38.000s	751.863us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	93.856us	50	50	100.00
V2	stress	aes_stress	28.000s	900.760us	50	50	100.00
V2	sideload	aes_stress	28.000s	900.760us	50	50	100.00
		aes_sideload	30.000s	922.100us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	717.244us	50	50	100.00
V2	stress_all	aes_stress_all	15.850m	27.341ms	10	10	100.00
V2	alert_test	aes_alert_test	14.000s	63.817us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	1.046ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	1.046ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	99.049us	5	5	100.00
		aes_csr_rw	4.000s	63.705us	20	20	100.00
		aes_csr_aliasing	5.000s	273.042us	5	5	100.00
		aes_same_csr_outstanding	8.000s	93.351us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	99.049us	5	5	100.00
		aes_csr_rw	4.000s	63.705us	20	20	100.00
		aes_csr_aliasing	5.000s	273.042us	5	5	100.00
		aes_same_csr_outstanding	8.000s	93.351us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	27.000s	956.218us	49	50	98.00
V2S	fault_inject	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	220.578us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	504.498us	5	5	100.00
		aes_tl_intg_err	9.000s	759.723us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	759.723us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	93.856us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	86.651us	50	50	100.00
		aes_stress	28.000s	900.760us	50	50	100.00
		aes_alert_reset	15.000s	93.856us	50	50	100.00
		aes_core_fi	1.483m	10.033ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	170.177us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	78.943us	50	50	100.00
		aes_stress	28.000s	900.760us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	28.000s	900.760us	50	50	100.00
		aes_sideload	30.000s	922.100us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	78.943us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	78.943us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	78.943us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	78.943us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	78.943us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	28.000s	900.760us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	28.000s	900.760us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.300m	7.744ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.300m	7.744ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.007ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.300m	7.744ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	93.856us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_ctr_fi	19.000s	145.299us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.300m	7.744ms	49	50	98.00
		aes_control_fi	48.000s	10.010ms	284	300	94.67
		aes_cipher_fi	48.000s	10.007ms	334	350	95.43
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.983m	5.030ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.53	96.25	99.42	95.85	97.72	97.78	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test aes_control_fi has 9 failures.
  - 11.aes_control_fi.114929747736759625592266475857204153780265941101461117106590869426013980751386
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job ID: smart:8077b025-cf4a-40bf-983d-a65d86d220e2
```
  - 12.aes_control_fi.38355272637422129748723124131237977603781510258890294571233445668203375427300
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:753f15f7-aa12-400b-8fad-20b40084d7a2
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 4 failures.
  - 52.aes_cipher_fi.93704932388299373846923752454689540947080750655817406273763719752629392302578
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  Job ID: smart:59686519-3785-4a14-a58b-53f37f475732
```
  - 123.aes_cipher_fi.22417378818738077214828830995455090668669533966620422136606536169486801771964
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/123.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7a730be3-4280-415b-81f4-db68e7fc0a6c
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 3.aes_cipher_fi.13759669437493259776687147209929515750935343815453371365715516503372142318975
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019207547 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019207547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.aes_cipher_fi.3240412600116016103170797385799884941814823879089626889123710748576630882316
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10145046848 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10145046848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.22361813149483005029546590253346367604968794745767795530181705029327834874362
Line 800, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1590706200 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1590706200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.113157672843805079716673212808485597578463440587208331660410803309623600420961
Line 1495, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3140633837 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3140633837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 1.aes_control_fi.65764031440517777772370854170147767352577830760133632679470278150226589280937
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011775877 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011775877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_control_fi.38484154035537892686360471223180507454582785081240484027538997559381809436705
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10024899130 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024899130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 19.aes_core_fi.8214398767083445014950498386506129501264203272114394312092784312847340047640
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004128456 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004128456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_core_fi.10368858858561192382969230998124970594070187534855791885071133763920044104468
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10168525102 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10168525102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.30390974096320852757676140065831844633227480022664779255580700892931284396559
Line 1752, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1704075647 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1704075647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.27380772621827888259181815923598303096501467939657055026429297624581574262397
Line 999, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1830798130 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1830798130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 0.aes_fi.67625219431039864391185289218961589694528169051581011322868539503828425929655
    Line 13130, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_fi/latest/run.log
```
  UVM_FATAL @ 107834927 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 107834927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 46.aes_reseed.3470065233128135269834603988245183445284022428990144162789478910428170115540
    Line 2105, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_reseed/latest/run.log
```
  UVM_FATAL @ 173085252 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 173085252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```