AES/MASKED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	74.683us	1	1	100.00
V1	smoke	aes_smoke	9.000s	250.097us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	62.081us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	75.201us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.195ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	167.277us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	125.216us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	75.201us	20	20	100.00
		aes_csr_aliasing	4.000s	167.277us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	250.097us	50	50	100.00
		aes_config_error	1.083m	1.821ms	50	50	100.00
		aes_stress	38.000s	3.591ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	250.097us	50	50	100.00
		aes_config_error	1.083m	1.821ms	50	50	100.00
		aes_stress	38.000s	3.591ms	50	50	100.00
V2	back2back	aes_stress	38.000s	3.591ms	50	50	100.00
		aes_b2b	35.000s	391.665us	50	50	100.00
V2	backpressure	aes_stress	38.000s	3.591ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	250.097us	50	50	100.00
		aes_config_error	1.083m	1.821ms	50	50	100.00
		aes_stress	38.000s	3.591ms	50	50	100.00
		aes_alert_reset	15.000s	2.000ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	81.703us	50	50	100.00
		aes_config_error	1.083m	1.821ms	50	50	100.00
		aes_alert_reset	15.000s	2.000ms	50	50	100.00
V2	trigger_clear_test	aes_clear	50.000s	2.766ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	174.341us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	2.000ms	50	50	100.00
V2	stress	aes_stress	38.000s	3.591ms	50	50	100.00
V2	sideload	aes_stress	38.000s	3.591ms	50	50	100.00
		aes_sideload	17.000s	482.755us	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	352.737us	50	50	100.00
V2	stress_all	aes_stress_all	5.000m	9.982ms	10	10	100.00
V2	alert_test	aes_alert_test	10.000s	60.976us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	114.934us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	114.934us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	62.081us	5	5	100.00
		aes_csr_rw	3.000s	75.201us	20	20	100.00
		aes_csr_aliasing	4.000s	167.277us	5	5	100.00
		aes_same_csr_outstanding	4.000s	62.829us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	62.081us	5	5	100.00
		aes_csr_rw	3.000s	75.201us	20	20	100.00
		aes_csr_aliasing	4.000s	167.277us	5	5	100.00
		aes_same_csr_outstanding	4.000s	62.829us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.400m	2.898ms	50	50	100.00
V2S	fault_inject	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	14.000s	225.787us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	38.000s	4.170ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.232ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.232ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	2.000ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	250.097us	50	50	100.00
		aes_stress	38.000s	3.591ms	50	50	100.00
		aes_alert_reset	15.000s	2.000ms	50	50	100.00
		aes_core_fi	46.000s	10.016ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	114.233us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	64.498us	50	50	100.00
		aes_stress	38.000s	3.591ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	3.591ms	50	50	100.00
		aes_sideload	17.000s	482.755us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	64.498us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	64.498us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	64.498us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	64.498us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	64.498us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	3.591ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	3.591ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	49.000s	1.751ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	49.000s	1.751ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	27.000s	10.059ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	49.000s	1.751ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	2.000ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_ctr_fi	13.000s	57.598us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	49.000s	1.751ms	49	50	98.00
		aes_control_fi	49.000s	10.014ms	288	300	96.00
		aes_cipher_fi	27.000s	10.059ms	336	350	96.00
V2S		TOTAL			957	985	97.16
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.033m	79.007ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1564	1602	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	98.51	96.21	99.38	95.82	97.64	97.78	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_cipher_fi has 7 failures.
  - 66.aes_cipher_fi.3988451380080916226588801263025576605255057329042253788908828468046177691538
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a30e688b-2bd2-4e3c-8514-422a28bcc684
```
  - 123.aes_cipher_fi.65185745320352998450158351622562602753630272663423532218819133796029764453172
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/123.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2bb9234b-9dfc-4372-a27f-034a7545e533
```
  - ... and 5 more failures.
- Test aes_control_fi has 9 failures.
  - 104.aes_control_fi.88320141474194670977886608438199027214302925130475220479641446744295068422342
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_control_fi/latest/run.log
```
  Job ID: smart:bd9943e1-d1a6-4fa8-a15e-74174fb2eb54
```
  - 105.aes_control_fi.99379645741167732405180407746319278098424746988108686051116543827836541869846
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/105.aes_control_fi/latest/run.log
```
  Job ID: smart:eb2d5ddc-f511-4f08-a0a0-0836b96396e9
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.88392940505059772684533280288166427190638882026386793416564768554772915612720
Line 794, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 601455833 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 601455833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.28470432239553141318112507942176026061076695351728272807279337740913218763052
Line 1629, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3257775930 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3257775930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 1.aes_cipher_fi.65072890079379925904373395495748053048829917256108904234102324908391176142753
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012636745 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012636745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.aes_cipher_fi.56602953276517737020264031693681676886623671082622047019483504565197593748629
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/80.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10048403839 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048403839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 144.aes_control_fi.101413418778150269500268250976496571989310228682988296958924980566982367617621
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/144.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013837942 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013837942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 173.aes_control_fi.115341697385443262034937245060214249791864835154351803509457013329822057471331
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/173.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017438018 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017438018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

3.aes_stress_all_with_rand_reset.15232755239104449578234254836622006270774219144174664516184050540441505530358
Line 1073, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2135910376 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2135910376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.23693742041879125340021512232754932121683556479767731218641207097834620420105
Line 939, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3816551499 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3816551499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 15.aes_fi.78759914893229815496922114797581283476334318611107690302388815006766801795242
    Line 8217, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_fi/latest/run.log
```
  UVM_FATAL @  88477736 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  88477736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.36634895447618096392919447377092555560880309888906521680053978281949470647318
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015645088 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015645088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```