AES/MASKED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	96.390us	1	1	100.00
V1	smoke	aes_smoke	8.000s	183.382us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	60.277us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	69.912us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	15.000s	2.418ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	134.338us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	70.405us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	69.912us	20	20	100.00
		aes_csr_aliasing	5.000s	134.338us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	183.382us	50	50	100.00
		aes_config_error	19.000s	324.262us	50	50	100.00
		aes_stress	15.000s	356.297us	50	50	100.00
V2	key_length	aes_smoke	8.000s	183.382us	50	50	100.00
		aes_config_error	19.000s	324.262us	50	50	100.00
		aes_stress	15.000s	356.297us	50	50	100.00
V2	back2back	aes_stress	15.000s	356.297us	50	50	100.00
		aes_b2b	2.000m	1.179ms	50	50	100.00
V2	backpressure	aes_stress	15.000s	356.297us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	183.382us	50	50	100.00
		aes_config_error	19.000s	324.262us	50	50	100.00
		aes_stress	15.000s	356.297us	50	50	100.00
		aes_alert_reset	1.217m	4.710ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	76.434us	50	50	100.00
		aes_config_error	19.000s	324.262us	50	50	100.00
		aes_alert_reset	1.217m	4.710ms	50	50	100.00
V2	trigger_clear_test	aes_clear	21.000s	1.178ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	19.000s	296.119us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.217m	4.710ms	50	50	100.00
V2	stress	aes_stress	15.000s	356.297us	50	50	100.00
V2	sideload	aes_stress	15.000s	356.297us	50	50	100.00
		aes_sideload	23.000s	1.055ms	50	50	100.00
V2	deinitialization	aes_deinit	1.683m	5.085ms	50	50	100.00
V2	stress_all	aes_stress_all	4.667m	8.481ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	76.977us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	194.220us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	194.220us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	60.277us	5	5	100.00
		aes_csr_rw	7.000s	69.912us	20	20	100.00
		aes_csr_aliasing	5.000s	134.338us	5	5	100.00
		aes_same_csr_outstanding	8.000s	168.764us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	60.277us	5	5	100.00
		aes_csr_rw	7.000s	69.912us	20	20	100.00
		aes_csr_aliasing	5.000s	134.338us	5	5	100.00
		aes_same_csr_outstanding	8.000s	168.764us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	28.000s	845.123us	50	50	100.00
V2S	fault_inject	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	151.512us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	669.661us	5	5	100.00
		aes_tl_intg_err	9.000s	276.753us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	276.753us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.217m	4.710ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	183.382us	50	50	100.00
		aes_stress	15.000s	356.297us	50	50	100.00
		aes_alert_reset	1.217m	4.710ms	50	50	100.00
		aes_core_fi	1.650m	10.003ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	17.000s	152.326us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	324.851us	50	50	100.00
		aes_stress	15.000s	356.297us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	356.297us	50	50	100.00
		aes_sideload	23.000s	1.055ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	324.851us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	324.851us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	324.851us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	324.851us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	324.851us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	356.297us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	356.297us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.800m	2.872ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.800m	2.872ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.006ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.800m	2.872ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.217m	4.710ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_ctr_fi	5.000s	343.624us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.800m	2.872ms	50	50	100.00
		aes_control_fi	45.000s	10.009ms	280	300	93.33
		aes_cipher_fi	50.000s	10.006ms	344	350	98.29
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.033m	8.921ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1562	1602	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.52	96.23	99.43	95.72	97.72	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_cipher_fi has 3 failures.
  - 11.aes_cipher_fi.74247681585977692804939890124870946470991666060891747572425984484531310578310
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4d10110a-1fa2-47d8-9a8d-c9f4cc074ed8
```
  - 28.aes_cipher_fi.70487752678961177321193764741636165149865798502017992659070824992418491557190
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:518dea11-40db-4d31-b837-78e8c4ef249c
```
  - ... and 1 more failures.
- Test aes_control_fi has 14 failures.
  - 20.aes_control_fi.33530485345949446075706587250865815783284274412413999030097391836518298385234
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:1aceeecb-e7b6-4b14-a59b-94b53ad636fa
```
  - 59.aes_control_fi.54223642484043169599064209316228009403734802305521806979853532591141313215660
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  Job ID: smart:71770bab-c647-4bdd-abc1-b06554aafcc2
```
  - ... and 12 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.8482179634112637122242097447539383828496717588139828922671752858746487804512
Line 623, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8920857137 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 8920857137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.96355808379429328436826163734081520167839128587372156140654505415550511891456
Line 1780, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5918991660 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5918991660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 14.aes_control_fi.104657967536064969584665828982691281979857111569509761605475584159612079739994
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10042153144 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042153144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 102.aes_control_fi.76607971088664051245293368322269658349007957073505682171682142254080358016790
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/102.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10066496081 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10066496081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 1.aes_core_fi.48847951588193058920050315792089388999561243431542279254147852372895143784683
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10066309527 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10066309527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_core_fi.111227429320128167409273554595777985703355505339108742441978133659835424615700
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002955841 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002955841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 100.aes_cipher_fi.86189400621753719073807603792619672565999652996974492833192521626167620898618
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019906972 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019906972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 279.aes_cipher_fi.90843536193418024908963364986997493793694659209080889634294123265717678191038
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/279.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006434797 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006434797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.48527120478959047570344623299774770539979972495135005781810532058257035824967
    Line 380, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 214168346 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 214168346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.1904971807189314386495349154451662599810306963319979358762519013892755436283
    Line 888, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1486686304 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1486686304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.62045791040062306066918131470887935180126163630155718866265012678165106697816
    Line 619, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 228894553 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 228894553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.29602191309762781577515208543186422241571049392572352015162749578233378790754
    Line 379, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175694521 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 175694521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```