AES/MASKED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	57.309us	1	1	100.00
V1	smoke	aes_smoke	9.000s	255.843us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	94.954us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	52.688us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	3.202ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	88.460us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	106.193us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	52.688us	20	20	100.00
		aes_csr_aliasing	5.000s	88.460us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	255.843us	50	50	100.00
		aes_config_error	6.000s	234.443us	50	50	100.00
		aes_stress	40.000s	2.685ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	255.843us	50	50	100.00
		aes_config_error	6.000s	234.443us	50	50	100.00
		aes_stress	40.000s	2.685ms	50	50	100.00
V2	back2back	aes_stress	40.000s	2.685ms	50	50	100.00
		aes_b2b	33.000s	597.058us	50	50	100.00
V2	backpressure	aes_stress	40.000s	2.685ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	255.843us	50	50	100.00
		aes_config_error	6.000s	234.443us	50	50	100.00
		aes_stress	40.000s	2.685ms	50	50	100.00
		aes_alert_reset	32.000s	6.276ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	71.268us	50	50	100.00
		aes_config_error	6.000s	234.443us	50	50	100.00
		aes_alert_reset	32.000s	6.276ms	50	50	100.00
V2	trigger_clear_test	aes_clear	36.000s	1.056ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	189.913us	1	1	100.00
V2	reset_recovery	aes_alert_reset	32.000s	6.276ms	50	50	100.00
V2	stress	aes_stress	40.000s	2.685ms	50	50	100.00
V2	sideload	aes_stress	40.000s	2.685ms	50	50	100.00
		aes_sideload	20.000s	551.050us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	2.164ms	50	50	100.00
V2	stress_all	aes_stress_all	1.383m	3.984ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	74.108us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	367.547us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	367.547us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	94.954us	5	5	100.00
		aes_csr_rw	4.000s	52.688us	20	20	100.00
		aes_csr_aliasing	5.000s	88.460us	5	5	100.00
		aes_same_csr_outstanding	4.000s	151.687us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	94.954us	5	5	100.00
		aes_csr_rw	4.000s	52.688us	20	20	100.00
		aes_csr_aliasing	5.000s	88.460us	5	5	100.00
		aes_same_csr_outstanding	4.000s	151.687us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.800m	9.912ms	49	50	98.00
V2S	fault_inject	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	159.814us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	729.426us	5	5	100.00
		aes_tl_intg_err	5.000s	206.597us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	206.597us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	32.000s	6.276ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	255.843us	50	50	100.00
		aes_stress	40.000s	2.685ms	50	50	100.00
		aes_alert_reset	32.000s	6.276ms	50	50	100.00
		aes_core_fi	1.517m	10.004ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	203.831us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	56.101us	50	50	100.00
		aes_stress	40.000s	2.685ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	40.000s	2.685ms	50	50	100.00
		aes_sideload	20.000s	551.050us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	56.101us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	56.101us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	56.101us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	56.101us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	56.101us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	40.000s	2.685ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	40.000s	2.685ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	37.000s	1.945ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	37.000s	1.945ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.011ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	37.000s	1.945ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	32.000s	6.276ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_ctr_fi	18.000s	98.063us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	37.000s	1.945ms	50	50	100.00
		aes_control_fi	48.000s	10.007ms	284	300	94.67
		aes_cipher_fi	50.000s	10.011ms	341	350	97.43
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.467m	15.078ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1565	1602	97.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.42	95.83	97.72	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_cipher_fi has 2 failures.
  - 24.aes_cipher_fi.315704431067495034174664693776202291900654549089676548918974775752875424304
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job ID: smart:afbba2a2-3233-4b8f-ab85-7664aac48754
```
  - 337.aes_cipher_fi.101956052514828869374229034319467676465069423152198291926324701587828235157763
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/337.aes_cipher_fi/latest/run.log
```
  Job ID: smart:97d8b54d-e3b0-4643-bd4c-a3edecd34e21
```
- Test aes_control_fi has 14 failures.
  - 34.aes_control_fi.6290996630528820033783406333877202528247192574969315815449838880227049200955
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:a700e0f3-45a8-4eb5-a8ca-79c46e081347
```
  - 78.aes_control_fi.84071823478143880903732562146858890404615178153974692292065633980475702305680
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  Job ID: smart:efd2838c-7b3d-452b-9402-f7a959869cbe
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 76.aes_cipher_fi.22579276224675854627158960190928403983287483960996139954698859844816070433535
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005391821 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005391821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_cipher_fi.73405434488359516458808694718473629496291348717267476436786755239226092781196
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010846220 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010846220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.92592610579125608871131104943088960778234754105292131353488180818091039305889
Line 676, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 404579874 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 404579874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.57115411836106061185092637241565419431519644270670481657215238865978639283914
Line 1078, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2006620656 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2006620656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.10103538119698008822613003314440170777242924760140768418433686685721382453334
Line 1310, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 634379041 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 634379041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.9317433640369727707499714468474549327829786054795395771672496634419894084541
Line 959, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 795006733 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 795006733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 127.aes_control_fi.39774401640719068201405092714069717514040889446356691433218324083797005190739
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/127.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006523124 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006523124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 279.aes_control_fi.56038108329493537623571866210694214779150000777232147947690166062164429543380
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/279.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10051289967 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051289967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 9.aes_reseed.2934273155207481651815094496693734453793214492016722711193823315912440065625
    Line 1466, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_reseed/latest/run.log
```
  UVM_FATAL @  58385177 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  58385177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.96920949843637221851822562510461162415139555390379504636210207216527553045925
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003998794 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003998794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```