AES/MASKED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	616.814us	1	1	100.00
V1	smoke	aes_smoke	8.000s	75.440us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	83.859us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	53.713us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	3.331ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	135.094us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	150.060us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	53.713us	20	20	100.00
		aes_csr_aliasing	9.000s	135.094us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	75.440us	50	50	100.00
		aes_config_error	1.200m	2.779ms	50	50	100.00
		aes_stress	29.000s	807.784us	50	50	100.00
V2	key_length	aes_smoke	8.000s	75.440us	50	50	100.00
		aes_config_error	1.200m	2.779ms	50	50	100.00
		aes_stress	29.000s	807.784us	50	50	100.00
V2	back2back	aes_stress	29.000s	807.784us	50	50	100.00
		aes_b2b	44.000s	558.897us	50	50	100.00
V2	backpressure	aes_stress	29.000s	807.784us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	75.440us	50	50	100.00
		aes_config_error	1.200m	2.779ms	50	50	100.00
		aes_stress	29.000s	807.784us	50	50	100.00
		aes_alert_reset	26.000s	1.226ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	324.858us	50	50	100.00
		aes_config_error	1.200m	2.779ms	50	50	100.00
		aes_alert_reset	26.000s	1.226ms	50	50	100.00
V2	trigger_clear_test	aes_clear	42.000s	1.305ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	656.131us	1	1	100.00
V2	reset_recovery	aes_alert_reset	26.000s	1.226ms	50	50	100.00
V2	stress	aes_stress	29.000s	807.784us	50	50	100.00
V2	sideload	aes_stress	29.000s	807.784us	50	50	100.00
		aes_sideload	26.000s	771.886us	50	50	100.00
V2	deinitialization	aes_deinit	46.000s	1.523ms	50	50	100.00
V2	stress_all	aes_stress_all	1.133m	3.783ms	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	515.836us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	241.640us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	241.640us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	83.859us	5	5	100.00
		aes_csr_rw	4.000s	53.713us	20	20	100.00
		aes_csr_aliasing	9.000s	135.094us	5	5	100.00
		aes_same_csr_outstanding	5.000s	135.319us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	83.859us	5	5	100.00
		aes_csr_rw	4.000s	53.713us	20	20	100.00
		aes_csr_aliasing	9.000s	135.094us	5	5	100.00
		aes_same_csr_outstanding	5.000s	135.319us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	25.000s	3.071ms	50	50	100.00
V2S	fault_inject	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	438.325us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	725.338us	5	5	100.00
		aes_tl_intg_err	9.000s	728.980us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	728.980us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	26.000s	1.226ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	75.440us	50	50	100.00
		aes_stress	29.000s	807.784us	50	50	100.00
		aes_alert_reset	26.000s	1.226ms	50	50	100.00
		aes_core_fi	53.000s	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	75.048us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	76.023us	50	50	100.00
		aes_stress	29.000s	807.784us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	29.000s	807.784us	50	50	100.00
		aes_sideload	26.000s	771.886us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	76.023us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	76.023us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	76.023us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	76.023us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	76.023us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	29.000s	807.784us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	29.000s	807.784us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	33.000s	2.791ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	33.000s	2.791ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.022ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	33.000s	2.791ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	26.000s	1.226ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_ctr_fi	9.000s	72.550us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	33.000s	2.791ms	50	50	100.00
		aes_control_fi	47.000s	10.038ms	273	300	91.00
		aes_cipher_fi	50.000s	10.022ms	343	350	98.00
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.183m	914.180us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.54	96.28	99.41	95.74	97.72	100.00	99.11	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 18 failures.
  - 25.aes_control_fi.105959407952111436827446852171240344434237049328156738008390587313035528466833
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:3c0658e7-eded-460d-a39e-f95ee55865b8
```
  - 26.aes_control_fi.78324053733129844238139446859434364445926315726368977940687150999973110583678
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:ffc908de-5f8b-45e0-90fe-d321bb9a5086
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 3 failures.
  - 114.aes_cipher_fi.65030827419174910883058044031488342389583489870689265601802040889735447417659
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9d1f3434-61c6-4fbb-b4c3-77a4e97e4f4d
```
  - 147.aes_cipher_fi.36272927250625295632632631615374228689330924633902795911291231500198543046389
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/147.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2c4a9fff-270f-4937-a7c8-9db9eccc23f3
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.52987208591625104937888421640856257407518044034575212997124721925796450411288
Line 645, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 552008495 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 552008495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.58045073868476280191224584690886044227855427169327193967098534195785720089541
Line 1516, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1760211404 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1760211404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 61.aes_control_fi.97821205079371698092495931539343788808580858954932745348046668355128818351821
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10048404389 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048404389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_control_fi.16370987950496206286072907829401197474913691423386997342785944858316199265567
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10037974597 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037974597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 79.aes_cipher_fi.49103402103180964171090784832076617359183177686205364729138519731819205936161
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013824454 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013824454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 93.aes_cipher_fi.17033211777808760714722092769247351534929303810195993518379674930621121934626
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012352719 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012352719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 7.aes_core_fi.72299513024823588110165582764131498234886393654373467819409010201306663119874
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006161177 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006161177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_core_fi.97438431460662744457567985532557652327854424917404305229546563394961300627065
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010806983 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010806983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.37277749082928167006328110707768948869187612428898820816099811504988305637242
    Line 1723, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 914180375 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 914180375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```