AES/MASKED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	95.817us	1	1	100.00
V1	smoke	aes_smoke	18.000s	2.620ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	73.751us	5	5	100.00
V1	csr_rw	aes_csr_rw	22.000s	10.075ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	186.991us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.233m	10.021ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	498.391us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	22.000s	10.075ms	19	20	95.00
		aes_csr_aliasing	6.233m	10.021ms	4	5	80.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	18.000s	2.620ms	50	50	100.00
		aes_config_error	9.000s	608.390us	50	50	100.00
		aes_stress	4.217m	8.145ms	50	50	100.00
V2	key_length	aes_smoke	18.000s	2.620ms	50	50	100.00
		aes_config_error	9.000s	608.390us	50	50	100.00
		aes_stress	4.217m	8.145ms	50	50	100.00
V2	back2back	aes_stress	4.217m	8.145ms	50	50	100.00
		aes_b2b	50.000s	602.491us	50	50	100.00
V2	backpressure	aes_stress	4.217m	8.145ms	50	50	100.00
V2	multi_message	aes_smoke	18.000s	2.620ms	50	50	100.00
		aes_config_error	9.000s	608.390us	50	50	100.00
		aes_stress	4.217m	8.145ms	50	50	100.00
		aes_alert_reset	12.000s	442.013us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	110.689us	50	50	100.00
		aes_config_error	9.000s	608.390us	50	50	100.00
		aes_alert_reset	12.000s	442.013us	50	50	100.00
V2	trigger_clear_test	aes_clear	22.000s	621.299us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	378.265us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	442.013us	50	50	100.00
V2	stress	aes_stress	4.217m	8.145ms	50	50	100.00
V2	sideload	aes_stress	4.217m	8.145ms	50	50	100.00
		aes_sideload	37.000s	1.081ms	50	50	100.00
V2	deinitialization	aes_deinit	19.000s	642.038us	50	50	100.00
V2	stress_all	aes_stress_all	1.100m	4.511ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	79.819us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	243.268us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	243.268us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	73.751us	5	5	100.00
		aes_csr_rw	22.000s	10.075ms	19	20	95.00
		aes_csr_aliasing	6.233m	10.021ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	211.144us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	73.751us	5	5	100.00
		aes_csr_rw	22.000s	10.075ms	19	20	95.00
		aes_csr_aliasing	6.233m	10.021ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	211.144us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.650m	7.523ms	48	50	96.00
V2S	fault_inject	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	104.596us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	917.844us	5	5	100.00
		aes_tl_intg_err	9.000s	712.625us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	712.625us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	442.013us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	2.620ms	50	50	100.00
		aes_stress	4.217m	8.145ms	50	50	100.00
		aes_alert_reset	12.000s	442.013us	50	50	100.00
		aes_core_fi	1.483m	10.213ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	114.102us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	53.043us	50	50	100.00
		aes_stress	4.217m	8.145ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.217m	8.145ms	50	50	100.00
		aes_sideload	37.000s	1.081ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	53.043us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	53.043us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	53.043us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	53.043us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	53.043us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.217m	8.145ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.217m	8.145ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	786.636us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	786.636us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	41.000s	10.008ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	786.636us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	442.013us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_ctr_fi	10.000s	68.285us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	786.636us	50	50	100.00
		aes_control_fi	45.000s	10.013ms	284	300	94.67
		aes_cipher_fi	41.000s	10.008ms	344	350	98.29
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.583m	7.287ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.29	98.47	96.12	99.39	95.72	97.72	97.78	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test aes_control_fi has 11 failures.
  - 0.aes_control_fi.116759673910919699367471617522794140241614220768840311055077895923621131072
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:6401f00d-958f-44a6-bfaf-f2ba6bd0b796
```
  - 10.aes_control_fi.37161591478264232082367158376653907118411329604447575618522027737056294607228
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:a3afffcb-aca4-4645-b8b7-c63cccf45489
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 2 failures.
  - 96.aes_cipher_fi.81449369591176182353309639214679111017658744291404764573021511386564944817926
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  Job ID: smart:40a1bb5d-9d42-4772-a76b-bf936eecfd76
```
  - 277.aes_cipher_fi.15945948250577237784166579386230406073114672358784227701656795087597671953823
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/277.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a14b3bdd-bde0-447d-9a2d-6b4af39cf0a0
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.19837796878795320342901325596368571314272413593506050475086409640292365565296
Line 876, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12793675187 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 12793675187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.71873839919693923368532105499059999912983947815868768806474770405570302408186
Line 398, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 168342808 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 168342808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 22.aes_core_fi.82831203217159370710393016168389568302709188051952663460869077887371393500962
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10213069037 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10213069037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.43437138549588079610482986064529804579922977407828329841537739045558309002778
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020517548 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020517548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 14.aes_control_fi.16564779690390190097772354035927446958548620347784801457708082667212817383045
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009910406 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009910406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_control_fi.51028284130906590382630552542170985961438163258667937197492982880922681755110
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10169411842 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10169411842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 114.aes_cipher_fi.28400017156780231395720990963914604786980238911583820324072128159719094224388
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008149580 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008149580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 145.aes_cipher_fi.103264955313088282173513682822217718403004913889852461681135857110663061262534
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/145.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020053548 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020053548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,858): Assertion AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

2.aes_core_fi.101000728759381200250650628632063218124316996410826366534698261463232619881260
Line 311, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,858): (time 10451071 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (2 cycles, starting 10431071 PS)
            (SecAllowForcingMasks && force_masks_i) || dec_key_gen_o == SP2V_HIGH)
                                                                                 |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 10451071 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 10431071 PS)
  UVM_ERROR @  10451071 ps: (aes_cipher_core.sv:858) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateSubBytes

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 2.aes_csr_aliasing.92208524346795592734064588099921000617351945006922072577819695264196060492726
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10020684559 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xb1c80c84, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 10020684559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 4.aes_reseed.36843642553831275700420089836177340109209901334343923931833873156189877023962
    Line 4301, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_reseed/latest/run.log
```
  UVM_FATAL @ 264637355 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 264637355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 4.aes_csr_rw.74852165926318078845792644963828179293296235583041183845996751264410531109867
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10074661726 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1750384, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 10074661726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 46.aes_reseed.93625901064238157986775736450334001185484653551484530719613380957112001472528
    Line 2034, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_reseed/latest/run.log
```
  UVM_FATAL @ 220876716 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 220876716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```