AES/MASKED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	135.329us	1	1	100.00
V1	smoke	aes_smoke	48.000s	1.512ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	163.799us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	68.085us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	6.649ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.450m	10.039ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	138.948us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	68.085us	20	20	100.00
		aes_csr_aliasing	6.450m	10.039ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	48.000s	1.512ms	50	50	100.00
		aes_config_error	19.000s	1.178ms	50	50	100.00
		aes_stress	18.000s	596.168us	50	50	100.00
V2	key_length	aes_smoke	48.000s	1.512ms	50	50	100.00
		aes_config_error	19.000s	1.178ms	50	50	100.00
		aes_stress	18.000s	596.168us	50	50	100.00
V2	back2back	aes_stress	18.000s	596.168us	50	50	100.00
		aes_b2b	31.000s	308.402us	50	50	100.00
V2	backpressure	aes_stress	18.000s	596.168us	50	50	100.00
V2	multi_message	aes_smoke	48.000s	1.512ms	50	50	100.00
		aes_config_error	19.000s	1.178ms	50	50	100.00
		aes_stress	18.000s	596.168us	50	50	100.00
		aes_alert_reset	1.400m	2.694ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	24.000s	1.053ms	50	50	100.00
		aes_config_error	19.000s	1.178ms	50	50	100.00
		aes_alert_reset	1.400m	2.694ms	50	50	100.00
V2	trigger_clear_test	aes_clear	26.000s	690.851us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	836.943us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.400m	2.694ms	50	50	100.00
V2	stress	aes_stress	18.000s	596.168us	50	50	100.00
V2	sideload	aes_stress	18.000s	596.168us	50	50	100.00
		aes_sideload	31.000s	2.104ms	50	50	100.00
V2	deinitialization	aes_deinit	1.733m	6.302ms	50	50	100.00
V2	stress_all	aes_stress_all	1.750m	2.699ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	60.147us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	490.343us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	490.343us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	163.799us	5	5	100.00
		aes_csr_rw	8.000s	68.085us	20	20	100.00
		aes_csr_aliasing	6.450m	10.039ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	396.966us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	163.799us	5	5	100.00
		aes_csr_rw	8.000s	68.085us	20	20	100.00
		aes_csr_aliasing	6.450m	10.039ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	396.966us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	18.000s	533.516us	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	466.747us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	4.431ms	5	5	100.00
		aes_tl_intg_err	6.000s	431.071us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	431.071us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.400m	2.694ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	48.000s	1.512ms	50	50	100.00
		aes_stress	18.000s	596.168us	50	50	100.00
		aes_alert_reset	1.400m	2.694ms	50	50	100.00
		aes_core_fi	14.000s	556.612us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	248.497us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	62.390us	50	50	100.00
		aes_stress	18.000s	596.168us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	596.168us	50	50	100.00
		aes_sideload	31.000s	2.104ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	62.390us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	62.390us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	62.390us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	62.390us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	62.390us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	596.168us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	596.168us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	5.219ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	5.219ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.023ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	5.219ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.400m	2.694ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_ctr_fi	7.000s	253.541us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	5.219ms	50	50	100.00
		aes_control_fi	47.000s	10.043ms	283	300	94.33
		aes_cipher_fi	46.000s	10.023ms	338	350	96.57
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.717m	21.289ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.54	96.30	99.42	95.76	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_control_fi has 12 failures.
  - 0.aes_control_fi.9080709066959041005933160948297971146416494838306809103529290340579833629065
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:f14fe846-7bb1-4eba-b2c9-7a689e8fd325
```
  - 17.aes_control_fi.109654598012983448239652307073356435257915486517590452649728647702995366373933
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:f95e0d5d-a5fb-4206-8a75-a5f437a27712
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 2 failures.
  - 192.aes_cipher_fi.112247129427327050600732537835260904028422237876784592615538651396566659208318
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/192.aes_cipher_fi/latest/run.log
```
  Job ID: smart:60a6539b-b49c-4dac-9f1b-0a8e1e337280
```
  - 295.aes_cipher_fi.62154904555096730807354106489205760687837746877365365274364804822418371700266
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/295.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9053e894-124f-4aa1-9759-548ab093f949
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 6.aes_cipher_fi.105305784655363974253463460748581937227404165880944366748180898339751299773831
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10028577542 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028577542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 81.aes_cipher_fi.53265421487322080293796101151898700924839146072395202518758530969553404867287
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/81.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011200517 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011200517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.100077437224153794316800519183077356764541721537508944569145052843483503852716
Line 612, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7138345693 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7138345693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.60915569833453042166631718539029215565399740551937171702067789708352895565554
Line 1420, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4977781709 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4977781709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 72.aes_control_fi.19082004056351959491431332047855823465677563687122232535484402420202621232960
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027717142 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027717142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_control_fi.16892079245213993200061450917072286636983115105049470610414776886064881645420
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005753788 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005753788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.110553259545495236181369144288968927789143020634280878420042554158064828471251
Line 1539, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2755957517 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2755957517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.92166231123158286405060345196840430084409132223220045423853944573395229481567
Line 1270, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1132524499 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1132524499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 1.aes_stress_all.64639474780314195632687989927157748471007734381562469046343631766328918876993
    Line 3964, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 244797633 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 244797633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 3.aes_csr_aliasing.113018290121901927045003371605139165629720773968051568711803940035801934065662
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10039372823 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x26274784) == 0x0
  UVM_INFO @ 10039372823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```