AES/MASKED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	104.373us	1	1	100.00
V1	smoke	aes_smoke	10.000s	126.538us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	61.023us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	60.413us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	535.883us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	232.613us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	96.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	60.413us	20	20	100.00
		aes_csr_aliasing	5.000s	232.613us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	126.538us	50	50	100.00
		aes_config_error	14.000s	697.516us	50	50	100.00
		aes_stress	22.000s	619.903us	50	50	100.00
V2	key_length	aes_smoke	10.000s	126.538us	50	50	100.00
		aes_config_error	14.000s	697.516us	50	50	100.00
		aes_stress	22.000s	619.903us	50	50	100.00
V2	back2back	aes_stress	22.000s	619.903us	50	50	100.00
		aes_b2b	43.000s	455.855us	50	50	100.00
V2	backpressure	aes_stress	22.000s	619.903us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	126.538us	50	50	100.00
		aes_config_error	14.000s	697.516us	50	50	100.00
		aes_stress	22.000s	619.903us	50	50	100.00
		aes_alert_reset	44.000s	1.507ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	173.951us	50	50	100.00
		aes_config_error	14.000s	697.516us	50	50	100.00
		aes_alert_reset	44.000s	1.507ms	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	615.684us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.445ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	44.000s	1.507ms	50	50	100.00
V2	stress	aes_stress	22.000s	619.903us	50	50	100.00
V2	sideload	aes_stress	22.000s	619.903us	50	50	100.00
		aes_sideload	14.000s	341.761us	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	4.349ms	50	50	100.00
V2	stress_all	aes_stress_all	1.383m	3.113ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	515.692us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	317.654us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	317.654us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	61.023us	5	5	100.00
		aes_csr_rw	3.000s	60.413us	20	20	100.00
		aes_csr_aliasing	5.000s	232.613us	5	5	100.00
		aes_same_csr_outstanding	4.000s	126.769us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	61.023us	5	5	100.00
		aes_csr_rw	3.000s	60.413us	20	20	100.00
		aes_csr_aliasing	5.000s	232.613us	5	5	100.00
		aes_same_csr_outstanding	4.000s	126.769us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	28.000s	365.619us	50	50	100.00
V2S	fault_inject	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	259.246us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.486ms	5	5	100.00
		aes_tl_intg_err	5.000s	648.646us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	648.646us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	44.000s	1.507ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	126.538us	50	50	100.00
		aes_stress	22.000s	619.903us	50	50	100.00
		aes_alert_reset	44.000s	1.507ms	50	50	100.00
		aes_core_fi	1.450m	10.019ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	63.674us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	130.139us	50	50	100.00
		aes_stress	22.000s	619.903us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	22.000s	619.903us	50	50	100.00
		aes_sideload	14.000s	341.761us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	130.139us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	130.139us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	130.139us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	130.139us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	130.139us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	22.000s	619.903us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	22.000s	619.903us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	12.000s	604.451us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	12.000s	604.451us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.007ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	12.000s	604.451us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	44.000s	1.507ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_ctr_fi	8.000s	84.113us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	12.000s	604.451us	50	50	100.00
		aes_control_fi	49.000s	10.014ms	282	300	94.00
		aes_cipher_fi	49.000s	10.007ms	340	350	97.14
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	13.767m	40.935ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.26	98.47	96.12	99.38	95.58	97.64	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_cipher_fi has 2 failures.
  - 28.aes_cipher_fi.115270059658836661869182328851372645009023740404790844855402198258813670759469
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4580b789-1bbc-4cce-9b65-98f2c6fceaa7
```
  - 205.aes_cipher_fi.24576023686915531866676637964242362932854166542874043898495967049716372536789
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/205.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d50555ff-2323-4d96-b80e-3aff41f0da45
```
- Test aes_control_fi has 13 failures.
  - 51.aes_control_fi.89940928840564835233630891978500639648233037648437551830181858765971940154218
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:6d0560d3-ce3b-4507-a162-f22c1c2d6570
```
  - 97.aes_control_fi.49882833805749665259177967223704002599749956591629953934967565556071003680849
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  Job ID: smart:738be621-9276-4d0a-941b-a85f2196e973
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 30.aes_cipher_fi.85560463439247871940624751700781118156315070168679724681885733172891174689650
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10046322589 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046322589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.aes_cipher_fi.79058892300655890884445128499698306377090267566269688936367619295724553073793
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006670574 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006670574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.54950152839632824426741988742018844012964687092792084531994055178623524210883
Line 894, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40935074487 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 40935074487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.106919612070209798465341768967450969466328743883462547526318645478111188004700
Line 614, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 881284624 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 881284624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 13.aes_control_fi.15341669746096752637982183153585036018957768259454664199339954150961606117361
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013664920 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013664920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.aes_control_fi.44951346466796974101114616116326863973232321618399136630494225683550149715096
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012435983 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012435983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.19849760318804689986825642768906275141231240156747844815300353274021616461607
Line 1644, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3213869632 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3213869632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.29533366245087418817431605495366879174260581155421091628807569954958510772564
Line 1639, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1149203540 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1149203540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 10.aes_core_fi.46108318580354447176010352855793557348346998501935004532013386385477892955405
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008162660 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008162660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.aes_core_fi.31204067535880080050979776411104177545566811190385111682544258258429119896111
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009736996 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009736996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.