AES/MASKED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	255.348us	1	1	100.00
V1	smoke	aes_smoke	6.000s	245.297us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	176.992us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	60.694us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	3.055ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	179.706us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	851.431us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	60.694us	20	20	100.00
		aes_csr_aliasing	5.000s	179.706us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	245.297us	50	50	100.00
		aes_config_error	15.000s	1.502ms	50	50	100.00
		aes_stress	8.550m	11.862ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	245.297us	50	50	100.00
		aes_config_error	15.000s	1.502ms	50	50	100.00
		aes_stress	8.550m	11.862ms	50	50	100.00
V2	back2back	aes_stress	8.550m	11.862ms	50	50	100.00
		aes_b2b	1.200m	834.146us	50	50	100.00
V2	backpressure	aes_stress	8.550m	11.862ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	245.297us	50	50	100.00
		aes_config_error	15.000s	1.502ms	50	50	100.00
		aes_stress	8.550m	11.862ms	50	50	100.00
		aes_alert_reset	18.000s	538.771us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	244.829us	50	50	100.00
		aes_config_error	15.000s	1.502ms	50	50	100.00
		aes_alert_reset	18.000s	538.771us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.183m	4.010ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	21.000s	863.334us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	538.771us	50	50	100.00
V2	stress	aes_stress	8.550m	11.862ms	50	50	100.00
V2	sideload	aes_stress	8.550m	11.862ms	50	50	100.00
		aes_sideload	24.000s	889.232us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	473.155us	50	50	100.00
V2	stress_all	aes_stress_all	8.117m	83.197ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	89.032us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	146.137us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	146.137us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	176.992us	5	5	100.00
		aes_csr_rw	4.000s	60.694us	20	20	100.00
		aes_csr_aliasing	5.000s	179.706us	5	5	100.00
		aes_same_csr_outstanding	5.000s	150.292us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	176.992us	5	5	100.00
		aes_csr_rw	4.000s	60.694us	20	20	100.00
		aes_csr_aliasing	5.000s	179.706us	5	5	100.00
		aes_same_csr_outstanding	5.000s	150.292us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	46.000s	3.201ms	50	50	100.00
V2S	fault_inject	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	112.096us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	638.429us	5	5	100.00
		aes_tl_intg_err	5.000s	303.106us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	303.106us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	538.771us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	245.297us	50	50	100.00
		aes_stress	8.550m	11.862ms	50	50	100.00
		aes_alert_reset	18.000s	538.771us	50	50	100.00
		aes_core_fi	3.067m	10.026ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	91.227us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	343.127us	50	50	100.00
		aes_stress	8.550m	11.862ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.550m	11.862ms	50	50	100.00
		aes_sideload	24.000s	889.232us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	343.127us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	343.127us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	343.127us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	343.127us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	343.127us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.550m	11.862ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.550m	11.862ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.017m	5.909ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.017m	5.909ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.012ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.017m	5.909ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	538.771us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_ctr_fi	5.000s	224.635us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.017m	5.909ms	50	50	100.00
		aes_control_fi	49.000s	10.012ms	278	300	92.67
		aes_cipher_fi	47.000s	10.012ms	337	350	96.29
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.667m	30.699ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.42	95.83	97.72	97.78	99.11	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 15 failures.
  - 1.aes_control_fi.38230921181685918185149135030626741662912876034935959846897911550993896191465
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:88df36fc-e69e-43d4-be51-fe20b7022aef
```
  - 18.aes_control_fi.50394631100689622749351008723633630796480546343630678164595378395735010229634
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:972c658d-6bd8-4adf-98dd-8061b3b89072
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 6 failures.
  - 71.aes_cipher_fi.77714650466084007798284924302101897251853579342011908273118094307147066288420
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3d18ebf0-0645-45c5-b920-c51ed4dd2879
```
  - 108.aes_cipher_fi.69739357154913536999269179565449568679967002987306034043443061805509095285027
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/108.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0a0fb4cc-8c2d-4243-b263-4339e98a1ecd
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.104372809073353477520310086216504448229763219689152930800202461654829899381191
Line 851, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4473277657 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4473277657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.10486283716416918315657110534006070635523655325159801745118159773102828555534
Line 1710, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2448388264 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2448388264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 6.aes_cipher_fi.101780793382944740555430697827332504702096995056684112918164233538927919502451
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011422602 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011422602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 143.aes_cipher_fi.57634444381972335437349623366603318317910210208041807840199714777252754806904
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/143.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011748939 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011748939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 53.aes_control_fi.94498888706117803675328860287178500295599224864841504835753252464525750164852
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018263897 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018263897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 131.aes_control_fi.100024310358162378005848529161190538813831277744734865638380180194074646411003
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/131.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006305496 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006305496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 48.aes_core_fi.40727491048006983549554656287314147097589826285479525656460525497412978967530
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017890415 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017890415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_core_fi.5296816389469669659818466982438418622278248232147123113962942002473701138041
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008674511 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008674511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.59822021636019099331049190962364049485389305937122561105055203728028274189812
    Line 509, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 834927522 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 834860855 PS)
  UVM_ERROR @ 834927522 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 834927522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.41179469236132844629709178772150131870634898040146334253256154827645448367440
    Line 1246, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4787266267 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4787266267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.112667374020475637862685563192161437705288843822922867121239822274285496055398
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025758518 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xc46cb984) == 0x0
  UVM_INFO @ 10025758518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```