AES/MASKED Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.944us	1	1	100.00
V1	smoke	aes_smoke	11.000s	368.845us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	108.332us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	204.222us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.227ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	525.630us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	121.618us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	204.222us	20	20	100.00
		aes_csr_aliasing	5.000s	525.630us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	368.845us	50	50	100.00
		aes_config_error	19.000s	2.285ms	50	50	100.00
		aes_stress	9.000s	136.408us	50	50	100.00
V2	key_length	aes_smoke	11.000s	368.845us	50	50	100.00
		aes_config_error	19.000s	2.285ms	50	50	100.00
		aes_stress	9.000s	136.408us	50	50	100.00
V2	back2back	aes_stress	9.000s	136.408us	50	50	100.00
		aes_b2b	37.000s	475.561us	50	50	100.00
V2	backpressure	aes_stress	9.000s	136.408us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	368.845us	50	50	100.00
		aes_config_error	19.000s	2.285ms	50	50	100.00
		aes_stress	9.000s	136.408us	50	50	100.00
		aes_alert_reset	1.300m	13.955ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	99.390us	50	50	100.00
		aes_config_error	19.000s	2.285ms	50	50	100.00
		aes_alert_reset	1.300m	13.955ms	50	50	100.00
V2	trigger_clear_test	aes_clear	41.000s	1.152ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	483.109us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.300m	13.955ms	50	50	100.00
V2	stress	aes_stress	9.000s	136.408us	50	50	100.00
V2	sideload	aes_stress	9.000s	136.408us	50	50	100.00
		aes_sideload	42.000s	1.344ms	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	860.938us	50	50	100.00
V2	stress_all	aes_stress_all	2.333m	4.277ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	76.960us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	242.729us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	242.729us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	108.332us	5	5	100.00
		aes_csr_rw	3.000s	204.222us	20	20	100.00
		aes_csr_aliasing	5.000s	525.630us	5	5	100.00
		aes_same_csr_outstanding	5.000s	437.112us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	108.332us	5	5	100.00
		aes_csr_rw	3.000s	204.222us	20	20	100.00
		aes_csr_aliasing	5.000s	525.630us	5	5	100.00
		aes_same_csr_outstanding	5.000s	437.112us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	32.000s	1.011ms	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	295.647us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	1.369ms	5	5	100.00
		aes_tl_intg_err	5.000s	581.343us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	581.343us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.300m	13.955ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	368.845us	50	50	100.00
		aes_stress	9.000s	136.408us	50	50	100.00
		aes_alert_reset	1.300m	13.955ms	50	50	100.00
		aes_core_fi	5.067m	10.014ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	62.932us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	110.413us	50	50	100.00
		aes_stress	9.000s	136.408us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	136.408us	50	50	100.00
		aes_sideload	42.000s	1.344ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	110.413us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	110.413us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	110.413us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	110.413us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	110.413us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	136.408us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	136.408us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	873.082us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	873.082us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.014ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	873.082us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.300m	13.955ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_ctr_fi	8.000s	73.883us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	873.082us	49	50	98.00
		aes_control_fi	50.000s	10.020ms	284	300	94.67
		aes_cipher_fi	49.000s	10.014ms	336	350	96.00
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	59.000s	2.967ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.55	96.32	99.43	95.63	97.64	97.78	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_control_fi has 10 failures.
  - 20.aes_control_fi.3414686744049671893478577680123029005842553748109274746260704889636693405023
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:7f4d64ce-e7c9-438b-ab60-7986097f3de0
```
  - 21.aes_control_fi.81140172489647817697430661744616211945662939591892609505256466389565127799539
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:a757795e-4a9d-4e48-aea2-31b7c8d01fcd
```
  - ... and 8 more failures.
- Test aes_fi has 1 failures.
  - 46.aes_fi.71347327108849351485216305511723404962894346842263758072786046549135526474023
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_fi/latest/run.log
```
  Job ID: smart:d3806b72-5b05-48a1-b2c9-3a47e40b6b82
```
- Test aes_cipher_fi has 3 failures.
  - 147.aes_cipher_fi.81730642634620422555709305904886455557247585934386479665687263967707412385709
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/147.aes_cipher_fi/latest/run.log
```
  Job ID: smart:162fc678-9640-4e96-9057-27c2643ab00b
```
  - 207.aes_cipher_fi.88961550012608827725580258411251614271035363622839341172867448873053714974804
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/207.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b604c3e3-6ce1-4cbc-95af-7f008cd94c71
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 86.aes_cipher_fi.31513000313705695654247045402572472718230779171748496888101483458013496380415
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017375963 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017375963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 89.aes_cipher_fi.101215277470835201634914165912072922693803558906251812174397409094730484707483
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012236706 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012236706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.22340751559260678655462833109080720759670462680700615533112509848208166610238
Line 1211, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 769238695 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 769238695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.85657728266667350499160016358467315042770914155107164002331829026786086211267
Line 484, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1744019614 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1744019614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 11.aes_control_fi.8229916519240791009687884674580823804156388738360858936967440877934677379022
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020082262 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020082262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 103.aes_control_fi.21369888878390707263545876290139927860988893901635716000088622391885882688453
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10031038286 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031038286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

2.aes_stress_all_with_rand_reset.79212683505484934912234093250048700006345532408423841052172128238137549964548
Line 642, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 478630795 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 478630795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.64933879009318222792566719426616649301321206979277472711218327803723072626524
Line 1401, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2966552388 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2966552388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.72532057658806617234223183397615949220380732523154366350232339641994719945419
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030162764 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030162764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.aes_core_fi.95633485318846848617144811313567745454475481056426591961025870229245979522262
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005083007 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005083007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.30966349396889700290125139826535841581347325945910238058147903752334421787676
    Line 437, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 545039433 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 545039433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 66.aes_core_fi.98567474346045253192579983774838909383861896051028235966199405883587246851566
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/66.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014499812 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x10fb3d84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10014499812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```