AES/MASKED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.648us	1	1	100.00
V1	smoke	aes_smoke	14.000s	57.005us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	79.238us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	88.884us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.645ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	68.005us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	114.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	88.884us	20	20	100.00
		aes_csr_aliasing	4.000s	68.005us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	57.005us	50	50	100.00
		aes_config_error	14.000s	143.643us	50	50	100.00
		aes_stress	17.000s	2.142ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	57.005us	50	50	100.00
		aes_config_error	14.000s	143.643us	50	50	100.00
		aes_stress	17.000s	2.142ms	50	50	100.00
V2	back2back	aes_stress	17.000s	2.142ms	50	50	100.00
		aes_b2b	32.000s	763.359us	50	50	100.00
V2	backpressure	aes_stress	17.000s	2.142ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	57.005us	50	50	100.00
		aes_config_error	14.000s	143.643us	50	50	100.00
		aes_stress	17.000s	2.142ms	50	50	100.00
		aes_alert_reset	30.000s	1.913ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	12.000s	106.141us	50	50	100.00
		aes_config_error	14.000s	143.643us	50	50	100.00
		aes_alert_reset	30.000s	1.913ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.050m	3.642ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	203.306us	1	1	100.00
V2	reset_recovery	aes_alert_reset	30.000s	1.913ms	50	50	100.00
V2	stress	aes_stress	17.000s	2.142ms	50	50	100.00
V2	sideload	aes_stress	17.000s	2.142ms	50	50	100.00
		aes_sideload	15.000s	399.397us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	96.470us	50	50	100.00
V2	stress_all	aes_stress_all	1.350m	1.611ms	10	10	100.00
V2	alert_test	aes_alert_test	10.000s	88.532us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	443.239us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	443.239us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	79.238us	5	5	100.00
		aes_csr_rw	4.000s	88.884us	20	20	100.00
		aes_csr_aliasing	4.000s	68.005us	5	5	100.00
		aes_same_csr_outstanding	4.000s	67.427us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	79.238us	5	5	100.00
		aes_csr_rw	4.000s	88.884us	20	20	100.00
		aes_csr_aliasing	4.000s	68.005us	5	5	100.00
		aes_same_csr_outstanding	4.000s	67.427us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	24.000s	1.269ms	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	778.596us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	793.343us	5	5	100.00
		aes_tl_intg_err	8.000s	82.902us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	82.902us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	30.000s	1.913ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	57.005us	50	50	100.00
		aes_stress	17.000s	2.142ms	50	50	100.00
		aes_alert_reset	30.000s	1.913ms	50	50	100.00
		aes_core_fi	35.000s	3.099ms	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	251.937us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	63.505us	50	50	100.00
		aes_stress	17.000s	2.142ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	17.000s	2.142ms	50	50	100.00
		aes_sideload	15.000s	399.397us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	63.505us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	63.505us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	63.505us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	63.505us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	63.505us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	17.000s	2.142ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	17.000s	2.142ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	439.360us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	439.360us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.010ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	439.360us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	30.000s	1.913ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_ctr_fi	13.000s	53.492us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	439.360us	50	50	100.00
		aes_control_fi	18.000s	54.682us	286	300	95.33
		aes_cipher_fi	46.000s	10.010ms	335	350	95.71
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.900m	10.627ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.52	96.23	99.45	95.76	97.64	100.00	98.96	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test aes_control_fi has 14 failures.
  - 26.aes_control_fi.86886432377799984149146746176721303819151736141506184048572509104867241107985
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:6cb5317d-08c8-4736-9a09-d51c83bf508f
```
  - 29.aes_control_fi.38113294680170742996896297792249461608620003016543929850931098732451885717388
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job ID: smart:b6624c3e-f8d4-443c-87db-289fa8ea3149
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 5 failures.
  - 40.aes_cipher_fi.49266813279366648825101113904508593171059163162765894573247669723985076225464
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1227a543-5357-49a3-abfc-169d401a19e9
```
  - 82.aes_cipher_fi.1629477333421181256617343673047892130984713173830102047635797008329246279129
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6798346c-8913-4710-a802-db0ee4e36d8a
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 1.aes_cipher_fi.56409415985526032940751838506018514641535797861588458249573596016695314098409
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013842491 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013842491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.aes_cipher_fi.65254404793981247446403731867694496653313251252730417631518458267383223389344
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008466529 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008466529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.77347203456738789183369029629767163069181776869317834502349721912704460791304
Line 629, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5528640768 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5528640768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.110420856513257033050096544143963453637868094366210950264085478187682257736479
Line 490, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2502989805 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2502989805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

5.aes_stress_all_with_rand_reset.23816671525516658955642712820175001804252645247294800915554223398799679453552
Line 757, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 605731012 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 605731012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.65230092409352910684849077697990696935642760897956376130447920692423563999557
Line 1249, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1293014045 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1293014045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.75077411684089324060112774683014639783976800869537229563982293843948533665556
    Line 1077, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10626666165 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10626666165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```