AES/MASKED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	55.738us	1	1	100.00
V1	smoke	aes_smoke	1.983m	53.960us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.017m	111.787us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.050m	58.578us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	2.067m	119.738us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	2.050m	283.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.617m	65.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.050m	58.578us	20	20	100.00
		aes_csr_aliasing	2.050m	283.635us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.983m	53.960us	50	50	100.00
		aes_config_error	2.033m	88.606us	50	50	100.00
		aes_stress	3.767m	564.270us	50	50	100.00
V2	key_length	aes_smoke	1.983m	53.960us	50	50	100.00
		aes_config_error	2.033m	88.606us	50	50	100.00
		aes_stress	3.767m	564.270us	50	50	100.00
V2	back2back	aes_stress	3.767m	564.270us	50	50	100.00
		aes_b2b	2.267m	222.518us	50	50	100.00
V2	backpressure	aes_stress	3.767m	564.270us	50	50	100.00
V2	multi_message	aes_smoke	1.983m	53.960us	50	50	100.00
		aes_config_error	2.033m	88.606us	50	50	100.00
		aes_stress	3.767m	564.270us	50	50	100.00
		aes_alert_reset	1.933m	104.231us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.650m	62.978us	50	50	100.00
		aes_config_error	2.033m	88.606us	50	50	100.00
		aes_alert_reset	1.933m	104.231us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.950m	302.526us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	573.316us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.933m	104.231us	50	50	100.00
V2	stress	aes_stress	3.767m	564.270us	50	50	100.00
V2	sideload	aes_stress	3.767m	564.270us	50	50	100.00
		aes_sideload	3.217m	173.472us	50	50	100.00
V2	deinitialization	aes_deinit	2.000m	2.388ms	50	50	100.00
V2	stress_all	aes_stress_all	1.650m	9.258ms	10	10	100.00
V2	alert_test	aes_alert_test	2.133m	56.278us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.133m	139.792us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.133m	139.792us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.017m	111.787us	5	5	100.00
		aes_csr_rw	2.050m	58.578us	20	20	100.00
		aes_csr_aliasing	2.050m	283.635us	5	5	100.00
		aes_same_csr_outstanding	2.033m	222.520us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.017m	111.787us	5	5	100.00
		aes_csr_rw	2.050m	58.578us	20	20	100.00
		aes_csr_aliasing	2.050m	283.635us	5	5	100.00
		aes_same_csr_outstanding	2.033m	222.520us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.633m	89.551us	50	50	100.00
V2S	fault_inject	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.967m	105.177us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	17.000s	2.137ms	5	5	100.00
		aes_tl_intg_err	2.050m	230.017us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.050m	230.017us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.933m	104.231us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.983m	53.960us	50	50	100.00
		aes_stress	3.767m	564.270us	50	50	100.00
		aes_alert_reset	1.933m	104.231us	50	50	100.00
		aes_core_fi	1.883m	420.325us	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.067m	103.818us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.983m	73.123us	50	50	100.00
		aes_stress	3.767m	564.270us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.767m	564.270us	50	50	100.00
		aes_sideload	3.217m	173.472us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.983m	73.123us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.983m	73.123us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.983m	73.123us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.983m	73.123us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.983m	73.123us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.767m	564.270us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.767m	564.270us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.017m	362.709us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.017m	362.709us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	51.331us	229	350	65.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.017m	362.709us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.933m	104.231us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_ctr_fi	53.000s	79.560us	35	50	70.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.017m	362.709us	49	50	98.00
		aes_control_fi	1.017m	51.736us	181	300	60.33
		aes_cipher_fi	1.017m	51.331us	229	350	65.43
V2S		TOTAL			726	985	73.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.000s	563.978us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1333	1602	83.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.52	96.23	99.43	95.61	97.64	97.78	99.11	97.01

Failure Buckets

Job timed out after * minutes has 248 failures:
- Test aes_cipher_fi has 118 failures.
  - 12.aes_cipher_fi.22302986284822390087492202655476727877309145764290002012838022700879869509837
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_cipher_fi.86405644078972569788735002281084651942086901501874206794703119158676228505847
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 116 more failures.
- Test aes_ctr_fi has 15 failures.
  - 12.aes_ctr_fi.71017044488322653020265892937239345344249705597615437785411543868896026510301
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/12.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_ctr_fi.104512258198314529269421253686201641378670232518461782688341199725359509792685
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
- Test aes_control_fi has 115 failures.
  - 13.aes_control_fi.58446285028047047229636120050416995180811844005713002885168136907334545012183
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_control_fi.19710620681040082399237205053079370223952278039746061863454565412965759888309
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 113 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.90091921995102078769366687482432654163521218552900210022779432231831882405607
Line 478, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 189158593 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 189158593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.92833509338068616544142188466606555971627078740269335899291928470080241944593
Line 669, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 563978482 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 563978482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 7.aes_control_fi.23810671131789935124716052558562594220651970643956675250882537608232198211899
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10024937047 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024937047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_control_fi.107598635085142928575156063458634219529145839277032540990571126138761852979624
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004330821 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004330821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 21.aes_core_fi.6698922396704338605578149313531311176684717894550335559159658534537687948952
    Line 139, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006520865 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006520865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_core_fi.95245319778041509171431336954261828123125131685122050847390169471078090244401
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10037120548 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037120548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 54.aes_cipher_fi.81663479501161618162367842463693428651085814828383911076034789573315161234623
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10098645799 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10098645799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 86.aes_cipher_fi.85432102928065874839950817308448610668424316004559871624218878316460737444796
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005944231 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005944231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.86227465230299899065635346285281185566683241656104163174505109502072652459433
    Line 174, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30159908 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  30159908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.aes_stress_all_with_rand_reset.110643410101473143175279807268327081960034188186656776115026620792674719226441
    Line 520, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1104490196 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1104490196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.70293288549659618524662407221200596484641398374111662904640418375553056354761
    Line 359, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 697286411 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 697286411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 25.aes_fi.94706756445378389653756233959009178273608834361778626069638508346454082258791
    Line 6686, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_masked-sim-xcelium/25.aes_fi/latest/run.log
```
  UVM_FATAL @ 157190203 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 157190203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```